motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-12-18 13:38:36 -07:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/microblaze: Simplify compute_ldst_addr_type{a,b}

Browse source 
Require TCGv_i32 and TCGv be identical, so drop
the extensions.  Return constants when possible
instead of a mov into a temporary.  Return register
inputs unchanged when possible.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-12 13:56:32 -08:00
parent bd07403fc1
commit 36a9529e60
1 changed files with 13 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

26
target/microblaze/translate.c
View file

@ -606,19 +606,18 @@ DO_TYPEBI(xori, false, tcg_gen_xori_i32)
static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
{ {
TCGv ret = tcg_temp_new(); TCGv ret;
/* If any of the regs is r0, set t to the value of the other reg. */ /* If any of the regs is r0, set t to the value of the other reg. */
if (ra && rb) { if (ra && rb) {
TCGv_i32 tmp = tcg_temp_new_i32(); ret = tcg_temp_new_i32();
tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); tcg_gen_add_i32(ret, cpu_R[ra], cpu_R[rb]);
tcg_gen_extu_i32_tl(ret, tmp);
} else if (ra) { } else if (ra) {
tcg_gen_extu_i32_tl(ret, cpu_R[ra]); ret = cpu_R[ra];
} else if (rb) { } else if (rb) {
tcg_gen_extu_i32_tl(ret, cpu_R[rb]); ret = cpu_R[rb];
} else { } else {
tcg_gen_movi_tl(ret, 0); ret = tcg_constant_i32(0);
} }
if ((ra == 1 || rb == 1) && dc->cfg->stackprot) { if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
@ -629,15 +628,16 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
{ {
TCGv ret = tcg_temp_new(); TCGv ret;
/* If any of the regs is r0, set t to the value of the other reg. */ /* If any of the regs is r0, set t to the value of the other reg. */
if (ra) { if (ra && imm) {
TCGv_i32 tmp = tcg_temp_new_i32(); ret = tcg_temp_new_i32();
tcg_gen_addi_i32(tmp, cpu_R[ra], imm); tcg_gen_addi_i32(ret, cpu_R[ra], imm);
tcg_gen_extu_i32_tl(ret, tmp); } else if (ra) {
ret = cpu_R[ra];
} else { } else {
tcg_gen_movi_tl(ret, (uint32_t)imm); ret = tcg_constant_i32(imm);
} }
if (ra == 1 && dc->cfg->stackprot) { if (ra == 1 && dc->cfg->stackprot) {