target/riscv: Implement second stage MMU

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-01-31 17:02:56 -08:00 committed by Palmer Dabbelt
parent 1448689c7b
commit 36a18664ba
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2 changed files with 175 additions and 19 deletions

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@ -104,6 +104,7 @@ struct CPURISCVState {
target_ulong frm;
target_ulong badaddr;
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
target_ulong misa;