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target/riscv: Implement second stage MMU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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2 changed files with 175 additions and 19 deletions
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@ -104,6 +104,7 @@ struct CPURISCVState {
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target_ulong frm;
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target_ulong badaddr;
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target_ulong guest_phys_fault_addr;
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target_ulong priv_ver;
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target_ulong misa;
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