motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-26 11:32:23 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

amd_iommu: Use correct bitmask to set capability BAR

Browse source 
AMD IOMMU provides the base address of control registers through
IVRS table and PCI capability. Since this base address is of 64 bit,
use 32 bits mask (instead of 16 bits) to set BAR low and high.

Fixes: d29a09ca68 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Message-Id: <20250207045354.27329-3-sarunkod@amd.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Sairaj Kodilkar 2025-02-07 10:23:54 +05:30 • committed by Michael S. Tsirkin
parent 63dc0b8647
commit 3684717b74
2 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/i386/amd_iommu.c
View file

@ -1593,9 +1593,9 @@ static void amdvi_pci_realize(PCIDevice *pdev, Error **errp)
/* reset AMDVI specific capabilities, all r/o */ /* reset AMDVI specific capabilities, all r/o */
pci_set_long(pdev->config + s->capab_offset, AMDVI_CAPAB_FEATURES); pci_set_long(pdev->config + s->capab_offset, AMDVI_CAPAB_FEATURES);
pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_LOW,
AMDVI_BASE_ADDR & ~(0xffff0000)); AMDVI_BASE_ADDR & MAKE_64BIT_MASK(14, 18));
pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_HIGH, pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_HIGH,
(AMDVI_BASE_ADDR & ~(0xffff)) >> 16); AMDVI_BASE_ADDR >> 32);
pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_RANGE, pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_RANGE,
0xff000000); 0xff000000);
pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, 0); pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, 0);

2
hw/i386/amd_iommu.h
View file

@ -187,7 +187,7 @@
AMDVI_CAPAB_FLAG_HTTUNNEL | AMDVI_CAPAB_EFR_SUP) AMDVI_CAPAB_FLAG_HTTUNNEL | AMDVI_CAPAB_EFR_SUP)
/* AMDVI default address */ /* AMDVI default address */
#define AMDVI_BASE_ADDR 0xfed80000 #define AMDVI_BASE_ADDR 0xfed80000ULL
/* page management constants */ /* page management constants */
#define AMDVI_PAGE_SHIFT 12 #define AMDVI_PAGE_SHIFT 12