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sparc64: implement PCI and ISA irqs
Generate correct trap for external interrupts. Map PCI and ISA IRQs to RIC/UltraSPARC-IIi interrupt vectors. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
parent
89aaf60ded
commit
361dea401f
5 changed files with 93 additions and 38 deletions
48
hw/apb_pci.c
48
hw/apb_pci.c
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@ -66,6 +66,8 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#define RESET_WCMASK 0x98000000
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#define RESET_WMASK 0x60000000
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#define MAX_IVEC 0x30
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typedef struct APBState {
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SysBusDevice busdev;
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PCIBus *bus;
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@ -77,7 +79,8 @@ typedef struct APBState {
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t obio_irq_map[32];
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qemu_irq pci_irqs[32];
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qemu_irq *pbm_irqs;
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qemu_irq *ivec_irqs;
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uint32_t reset_control;
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unsigned int nr_resets;
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} APBState;
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@ -87,7 +90,7 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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{
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APBState *s = opaque;
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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@ -104,6 +107,12 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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}
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break;
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case 0x1000 ... 0x1080: /* OBIO interrupt control */
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if (addr & 4) {
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s->obio_irq_map[(addr & 0xff) >> 3] &= PBM_PCI_IMR_MASK;
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s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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s->pci_control[(addr & 0x3f) >> 2] = val;
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break;
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@ -154,6 +163,13 @@ static uint64_t apb_config_readl (void *opaque,
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val = 0;
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}
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break;
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case 0x1000 ... 0x1080: /* OBIO interrupt control */
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if (addr & 4) {
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val = s->obio_irq_map[(addr & 0xff) >> 3];
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} else {
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val = 0;
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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val = s->pci_control[(addr & 0x3f) >> 2];
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break;
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@ -190,7 +206,7 @@ static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
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APBState *s = opaque;
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val = qemu_bswap_len(val, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);
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pci_data_write(s->bus, addr, val, size);
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}
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@ -280,10 +296,19 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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if (irq_num < 32) {
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if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->pci_irqs[irq_num], level);
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qemu_set_irq(s->ivec_irqs[irq_num], level);
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->pci_irqs[irq_num]);
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qemu_irq_lower(s->ivec_irqs[irq_num]);
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}
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} else {
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/* OBIO IRQ map onto the next 16 INO. */
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if (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED) {
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->ivec_irqs[irq_num], level);
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->ivec_irqs[irq_num]);
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}
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}
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}
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@ -316,12 +341,12 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
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PCIBus *pci_apb_init(target_phys_addr_t special_base,
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target_phys_addr_t mem_base,
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qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
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qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
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qemu_irq **pbm_irqs)
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{
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DeviceState *dev;
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SysBusDevice *s;
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APBState *d;
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unsigned int i;
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PCIDevice *pci_dev;
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PCIBridge *br;
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@ -346,9 +371,8 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
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get_system_io(),
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0, 32);
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for (i = 0; i < 32; i++) {
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sysbus_connect_irq(s, i, pic[i]);
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}
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*pbm_irqs = d->pbm_irqs;
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d->ivec_irqs = ivec_irqs;
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pci_create_simple(d->bus, 0, "pbm-pci");
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@ -402,9 +426,7 @@ static int pci_pbm_init_device(SysBusDevice *dev)
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
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}
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for (i = 0; i < 32; i++) {
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sysbus_init_irq(dev, &s->pci_irqs[i]);
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}
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s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
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/* apb_config */
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memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
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