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target/arm: Convert SG

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-42-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:31 -07:00 • committed by Peter Maydell
parent 808092bbe3
commit 35d240acf1
2 changed files with 33 additions and 23 deletions
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5
target/arm/t32.decode
View file

@ -487,7 +487,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1
LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1
STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 {
SG 1110 1001 0111 1111 1110 1001 01111111
LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
}
# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch # Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch

51
target/arm/translate.c
View file

@ -8467,6 +8467,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a)
return true; return true;
} }
static bool trans_SG(DisasContext *s, arg_SG *a)
{
if (!arm_dc_feature(s, ARM_FEATURE_M) ||
!arm_dc_feature(s, ARM_FEATURE_V8)) {
return false;
}
/*
* SG (v8M only)
* The bulk of the behaviour for this instruction is implemented
* in v7m_handle_execute_nsc(), which deals with the insn when
* it is executed by a CPU in non-secure state from memory
* which is Secure & NonSecure-Callable.
* Here we only need to handle the remaining cases:
* * in NS memory (including the "security extension not
* implemented" case) : NOP
* * in S memory but CPU already secure (clear IT bits)
* We know that the attribute for the memory this insn is
* in must match the current CPU state, because otherwise
* get_phys_addr_pmsav8 would have generated an exception.
*/
if (s->v8m_secure) {
/* Like the IT insn, we don't need to generate any code */
s->condexec_cond = 0;
s->condexec_mask = 0;
}
return true;
}
/* /*
* Load/store register index * Load/store register index
*/ */
@ -10553,28 +10581,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
* - load/store doubleword, load/store exclusive, ldacq/strel, * - load/store doubleword, load/store exclusive, ldacq/strel,
* table branch, TT. * table branch, TT.
*/ */
if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) && if (insn & 0x01200000) {
arm_dc_feature(s, ARM_FEATURE_V8)) {
/* 0b1110_1001_0111_1111_1110_1001_0111_111
* - SG (v8M only)
* The bulk of the behaviour for this instruction is implemented
* in v7m_handle_execute_nsc(), which deals with the insn when
* it is executed by a CPU in non-secure state from memory
* which is Secure & NonSecure-Callable.
* Here we only need to handle the remaining cases:
* * in NS memory (including the "security extension not
* implemented" case) : NOP
* * in S memory but CPU already secure (clear IT bits)
* We know that the attribute for the memory this insn is
* in must match the current CPU state, because otherwise
* get_phys_addr_pmsav8 would have generated an exception.
*/
if (s->v8m_secure) {
/* Like the IT insn, we don't need to generate any code */
s->condexec_cond = 0;
s->condexec_mask = 0;
}
} else if (insn & 0x01200000) {
/* load/store dual, in decodetree */ /* load/store dual, in decodetree */
goto illegal_op; goto illegal_op;
} else if ((insn & (1 << 23)) == 0) { } else if ((insn & (1 << 23)) == 0) {