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hw/intc/aspeed: Add support for multiple output pins in INTC

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Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.

Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" function to connect source
orgates to INTC and INTC to GIC128 - GIC136. Updated the "aspeed_intc_realize"
function to initialize output pins.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-13-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:21 +08:00 • committed by Cédric Le Goater
parent 63f3618f9b
commit 35c909cd80
3 changed files with 12 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
hw/arm/aspeed_ast27x0.c
View file

@ -534,10 +534,14 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
sc->memmap[ASPEED_DEV_INTC]); sc->memmap[ASPEED_DEV_INTC]);
/* GICINT orgates -> INTC -> GIC */ /* source orgates -> INTC */
for (i = 0; i < ic->num_inpins; i++) { for (i = 0; i < ic->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
qdev_get_gpio_in(DEVICE(&a->intc), i)); qdev_get_gpio_in(DEVICE(&a->intc), i));
}
/* INTC -> GIC128 - GIC136 */
for (i = 0; i < ic->num_outpins; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
qdev_get_gpio_in(DEVICE(&a->gic), qdev_get_gpio_in(DEVICE(&a->gic),
aspeed_soc_ast2700_gic_intcmap[i].irq)); aspeed_soc_ast2700_gic_intcmap[i].irq));

4
hw/intc/aspeed_intc.c
View file

@ -347,6 +347,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) { if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
return; return;
} }
}
for (i = 0; i < aic->num_outpins; i++) {
sysbus_init_irq(sbd, &s->output_pins[i]); sysbus_init_irq(sbd, &s->output_pins[i]);
} }
} }
@ -391,6 +394,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2700 INTC Controller"; dc->desc = "ASPEED 2700 INTC Controller";
aic->num_lines = 32; aic->num_lines = 32;
aic->num_inpins = 9; aic->num_inpins = 9;
aic->num_outpins = 9;
aic->mem_size = 0x4000; aic->mem_size = 0x4000;
aic->nr_regs = 0x808 >> 2; aic->nr_regs = 0x808 >> 2;
aic->reg_offset = 0x1000; aic->reg_offset = 0x1000;

5
include/hw/intc/aspeed_intc.h
View file

@ -16,8 +16,8 @@
#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_NR_INTS 9
#define ASPEED_INTC_MAX_INPINS 9 #define ASPEED_INTC_MAX_INPINS 9
#define ASPEED_INTC_MAX_OUTPINS 9
struct AspeedINTCState { struct AspeedINTCState {
/*< private >*/ /*< private >*/
@ -29,7 +29,7 @@ struct AspeedINTCState {
uint32_t *regs; uint32_t *regs;
OrIRQState orgates[ASPEED_INTC_MAX_INPINS]; OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
qemu_irq output_pins[ASPEED_INTC_NR_INTS]; qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
uint32_t enable[ASPEED_INTC_MAX_INPINS]; uint32_t enable[ASPEED_INTC_MAX_INPINS];
uint32_t mask[ASPEED_INTC_MAX_INPINS]; uint32_t mask[ASPEED_INTC_MAX_INPINS];
@ -41,6 +41,7 @@ struct AspeedINTCClass {
uint32_t num_lines; uint32_t num_lines;
uint32_t num_inpins; uint32_t num_inpins;
uint32_t num_outpins;
uint64_t mem_size; uint64_t mem_size;
uint64_t nr_regs; uint64_t nr_regs;
uint64_t reg_offset; uint64_t reg_offset;