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aspeed/soc : Add AST1030 support

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The embedded core of AST1030 SoC is ARM Coretex M4.
It is hard to be integrated in the common Aspeed Soc framework.
We introduce a new ast1030 class with instance_init and realize
handlers.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: rename aspeed_ast10xx.c to aspeed_ast10x0.c to match zephyr ]
Message-Id: <20220401083850.15266-8-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Steven Lee 2022-05-02 17:03:03 +02:00 • committed by Cédric Le Goater
parent fa541a60dd
commit 356b230ed1
3 changed files with 307 additions and 1 deletions
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3
include/hw/arm/aspeed_soc.h
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@ -13,6 +13,7 @@
#define ASPEED_SOC_H
#include "hw/cpu/a15mpcore.h"
#include "hw/arm/armv7m.h"
#include "hw/intc/aspeed_vic.h"
#include "hw/misc/aspeed_scu.h"
#include "hw/adc/aspeed_adc.h"
@ -47,6 +48,7 @@ struct AspeedSoCState {
/*< public >*/
ARMCPU cpu[ASPEED_CPUS_NUM];
A15MPPrivState a7mpcore;
ARMv7MState armv7m;
MemoryRegion *dram_mr;
MemoryRegion sram;
AspeedVICState vic;
@ -72,6 +74,7 @@ struct AspeedSoCState {
AspeedSDHCIState emmc;
AspeedLPCState lpc;
uint32_t uart_default;
Clock *sysclk;
};
#define TYPE_ASPEED_SOC "aspeed-soc"