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target/openrisc: Implement EVBAR register

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Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.

The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).

Its presence is indicated by the EVBARP bit in the CPU Configuration
Register (CPUCFGR).

Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Tim 'mithro' Ansell 2017-04-18 16:15:50 +10:00 • committed by Stafford Horne
parent 1d7cf18d79
commit 356a2db3c6
4 changed files with 21 additions and 1 deletions
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2
target/openrisc/cpu.c
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@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj)
set_feature(cpu, OPENRISC_FEATURE_OB32S);
set_feature(cpu, OPENRISC_FEATURE_OF32S);
set_feature(cpu, OPENRISC_FEATURE_EVBAR);
}
static void openrisc_any_initfn(Object *obj)
@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj)
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
set_feature(cpu, OPENRISC_FEATURE_OB32S);
set_feature(cpu, OPENRISC_FEATURE_EVBAR);
}
typedef struct OpenRISCCPUInfo {