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target-ppc: Bug Fix: srawi

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For 64 bit implementations, the special case of a shift by zero
should result in the sign extension of the least significant 32 bits
of the source GPR (not a direct copy of the 64 bit source GPR).

Example:

R3 A6212433228F41DC
srawi 3,3,0
R3 expected : 00000000228F41DC
R3 actual   : A6212433228F41DC (without this patch)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta 2014-08-12 08:45:09 -05:00 • committed by Alexander Graf
parent 9824d01d5d
commit 34a0fad102
1 changed files with 1 additions and 1 deletions
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2
target-ppc/translate.c
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@ -1944,7 +1944,7 @@ static void gen_srawi(DisasContext *ctx)
TCGv dst = cpu_gpr[rA(ctx->opcode)]; TCGv dst = cpu_gpr[rA(ctx->opcode)];
TCGv src = cpu_gpr[rS(ctx->opcode)]; TCGv src = cpu_gpr[rS(ctx->opcode)];
if (sh == 0) { if (sh == 0) {
tcg_gen_mov_tl(dst, src); tcg_gen_ext32s_tl(dst, src);
tcg_gen_movi_tl(cpu_ca, 0); tcg_gen_movi_tl(cpu_ca, 0);
} else { } else {
TCGv t0; TCGv t0;