mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-08 02:03:56 -06:00
Merge remote-tracking branch 'qmp/queue/qmp' into staging
* qmp/queue/qmp: (29 commits) Add 'query-events' command to QMP to query async events qapi: convert netdev_del qapi: convert netdev_add net: net_client_init(): use error_set() net: purge the monitor object from all init functions qemu-config: introduce qemu_find_opts_err() qemu-config: find_list(): use error_set() qerror: introduce QERR_INVALID_OPTION_GROUP qemu-option: qemu_opts_from_qdict(): use error_set() qemu-option: introduce qemu_opt_set_err() qemu-option: opt_set(): use error_set() qemu-option: qemu_opts_validate(): use error_set() qemu-option: qemu_opt_parse(): use error_set() qemu-option: parse_option_size(): use error_set() qemu-option: parse_option_bool(): use error_set() qemu-option: parse_option_number(): use error_set() qemu-option: qemu_opts_create(): use error_set() introduce a new monitor command 'dump-guest-memory' to dump guest's memory make gdb_id() generally avialable and rename it to cpu_index() target-i386: Add API to get note's size ...
This commit is contained in:
Anthony Liguori
commit
349417004a
49 changed files with 2693 additions and 255 deletions
449
target-i386/arch_dump.c
Normal file
449
target-i386/arch_dump.c
Normal file
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|
@ -0,0 +1,449 @@
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|||
/*
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* i386 memory mapping
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*
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* Copyright Fujitsu, Corp. 2011, 2012
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*
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* Authors:
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* Wen Congyang <wency@cn.fujitsu.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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||||
*/
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#include "cpu.h"
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#include "cpu-all.h"
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#include "dump.h"
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#include "elf.h"
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#ifdef TARGET_X86_64
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typedef struct {
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target_ulong r15, r14, r13, r12, rbp, rbx, r11, r10;
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target_ulong r9, r8, rax, rcx, rdx, rsi, rdi, orig_rax;
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target_ulong rip, cs, eflags;
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target_ulong rsp, ss;
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target_ulong fs_base, gs_base;
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target_ulong ds, es, fs, gs;
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} x86_64_user_regs_struct;
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typedef struct {
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char pad1[32];
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uint32_t pid;
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char pad2[76];
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x86_64_user_regs_struct regs;
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char pad3[8];
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} x86_64_elf_prstatus;
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static int x86_64_write_elf64_note(write_core_dump_function f,
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CPUArchState *env, int id,
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void *opaque)
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{
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x86_64_user_regs_struct regs;
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Elf64_Nhdr *note;
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char *buf;
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int descsz, note_size, name_size = 5;
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const char *name = "CORE";
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int ret;
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regs.r15 = env->regs[15];
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regs.r14 = env->regs[14];
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regs.r13 = env->regs[13];
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regs.r12 = env->regs[12];
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regs.r11 = env->regs[11];
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regs.r10 = env->regs[10];
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regs.r9 = env->regs[9];
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regs.r8 = env->regs[8];
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regs.rbp = env->regs[R_EBP];
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regs.rsp = env->regs[R_ESP];
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regs.rdi = env->regs[R_EDI];
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regs.rsi = env->regs[R_ESI];
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regs.rdx = env->regs[R_EDX];
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regs.rcx = env->regs[R_ECX];
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regs.rbx = env->regs[R_EBX];
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regs.rax = env->regs[R_EAX];
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regs.rip = env->eip;
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regs.eflags = env->eflags;
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regs.orig_rax = 0; /* FIXME */
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regs.cs = env->segs[R_CS].selector;
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regs.ss = env->segs[R_SS].selector;
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regs.fs_base = env->segs[R_FS].base;
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regs.gs_base = env->segs[R_GS].base;
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regs.ds = env->segs[R_DS].selector;
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regs.es = env->segs[R_ES].selector;
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regs.fs = env->segs[R_FS].selector;
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regs.gs = env->segs[R_GS].selector;
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descsz = sizeof(x86_64_elf_prstatus);
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note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
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(descsz + 3) / 4) * 4;
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note = g_malloc(note_size);
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memset(note, 0, note_size);
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note->n_namesz = cpu_to_le32(name_size);
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note->n_descsz = cpu_to_le32(descsz);
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note->n_type = cpu_to_le32(NT_PRSTATUS);
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buf = (char *)note;
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buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
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memcpy(buf, name, name_size);
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buf += ((name_size + 3) / 4) * 4;
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memcpy(buf + 32, &id, 4); /* pr_pid */
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buf += descsz - sizeof(x86_64_user_regs_struct)-sizeof(target_ulong);
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memcpy(buf, ®s, sizeof(x86_64_user_regs_struct));
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ret = f(note, note_size, opaque);
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g_free(note);
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if (ret < 0) {
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return -1;
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}
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return 0;
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}
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#endif
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typedef struct {
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uint32_t ebx, ecx, edx, esi, edi, ebp, eax;
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unsigned short ds, __ds, es, __es;
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unsigned short fs, __fs, gs, __gs;
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uint32_t orig_eax, eip;
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unsigned short cs, __cs;
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uint32_t eflags, esp;
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unsigned short ss, __ss;
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} x86_user_regs_struct;
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typedef struct {
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char pad1[24];
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uint32_t pid;
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char pad2[44];
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x86_user_regs_struct regs;
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char pad3[4];
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} x86_elf_prstatus;
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static void x86_fill_elf_prstatus(x86_elf_prstatus *prstatus, CPUArchState *env,
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int id)
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{
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memset(prstatus, 0, sizeof(x86_elf_prstatus));
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prstatus->regs.ebp = env->regs[R_EBP] & 0xffffffff;
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prstatus->regs.esp = env->regs[R_ESP] & 0xffffffff;
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prstatus->regs.edi = env->regs[R_EDI] & 0xffffffff;
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prstatus->regs.esi = env->regs[R_ESI] & 0xffffffff;
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prstatus->regs.edx = env->regs[R_EDX] & 0xffffffff;
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prstatus->regs.ecx = env->regs[R_ECX] & 0xffffffff;
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prstatus->regs.ebx = env->regs[R_EBX] & 0xffffffff;
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prstatus->regs.eax = env->regs[R_EAX] & 0xffffffff;
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prstatus->regs.eip = env->eip & 0xffffffff;
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prstatus->regs.eflags = env->eflags & 0xffffffff;
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prstatus->regs.cs = env->segs[R_CS].selector;
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prstatus->regs.ss = env->segs[R_SS].selector;
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prstatus->regs.ds = env->segs[R_DS].selector;
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prstatus->regs.es = env->segs[R_ES].selector;
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prstatus->regs.fs = env->segs[R_FS].selector;
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prstatus->regs.gs = env->segs[R_GS].selector;
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prstatus->pid = id;
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}
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static int x86_write_elf64_note(write_core_dump_function f, CPUArchState *env,
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int id, void *opaque)
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{
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x86_elf_prstatus prstatus;
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Elf64_Nhdr *note;
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char *buf;
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int descsz, note_size, name_size = 5;
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const char *name = "CORE";
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int ret;
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x86_fill_elf_prstatus(&prstatus, env, id);
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descsz = sizeof(x86_elf_prstatus);
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note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
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(descsz + 3) / 4) * 4;
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note = g_malloc(note_size);
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memset(note, 0, note_size);
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note->n_namesz = cpu_to_le32(name_size);
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note->n_descsz = cpu_to_le32(descsz);
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note->n_type = cpu_to_le32(NT_PRSTATUS);
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buf = (char *)note;
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buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
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memcpy(buf, name, name_size);
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buf += ((name_size + 3) / 4) * 4;
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memcpy(buf, &prstatus, sizeof(prstatus));
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ret = f(note, note_size, opaque);
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g_free(note);
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if (ret < 0) {
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return -1;
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}
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return 0;
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}
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int cpu_write_elf64_note(write_core_dump_function f, CPUArchState *env,
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int cpuid, void *opaque)
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{
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int ret;
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#ifdef TARGET_X86_64
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bool lma = !!(first_cpu->hflags & HF_LMA_MASK);
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if (lma) {
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ret = x86_64_write_elf64_note(f, env, cpuid, opaque);
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} else {
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#endif
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ret = x86_write_elf64_note(f, env, cpuid, opaque);
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#ifdef TARGET_X86_64
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}
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#endif
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return ret;
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}
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int cpu_write_elf32_note(write_core_dump_function f, CPUArchState *env,
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int cpuid, void *opaque)
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{
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x86_elf_prstatus prstatus;
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Elf32_Nhdr *note;
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char *buf;
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int descsz, note_size, name_size = 5;
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const char *name = "CORE";
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int ret;
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x86_fill_elf_prstatus(&prstatus, env, cpuid);
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descsz = sizeof(x86_elf_prstatus);
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note_size = ((sizeof(Elf32_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
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(descsz + 3) / 4) * 4;
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note = g_malloc(note_size);
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memset(note, 0, note_size);
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note->n_namesz = cpu_to_le32(name_size);
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note->n_descsz = cpu_to_le32(descsz);
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note->n_type = cpu_to_le32(NT_PRSTATUS);
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buf = (char *)note;
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buf += ((sizeof(Elf32_Nhdr) + 3) / 4) * 4;
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memcpy(buf, name, name_size);
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buf += ((name_size + 3) / 4) * 4;
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memcpy(buf, &prstatus, sizeof(prstatus));
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ret = f(note, note_size, opaque);
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g_free(note);
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if (ret < 0) {
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return -1;
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}
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return 0;
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}
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/*
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* please count up QEMUCPUSTATE_VERSION if you have changed definition of
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* QEMUCPUState, and modify the tools using this information accordingly.
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*/
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#define QEMUCPUSTATE_VERSION (1)
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struct QEMUCPUSegment {
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uint32_t selector;
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uint32_t limit;
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uint32_t flags;
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uint32_t pad;
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uint64_t base;
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};
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typedef struct QEMUCPUSegment QEMUCPUSegment;
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struct QEMUCPUState {
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uint32_t version;
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uint32_t size;
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uint64_t rax, rbx, rcx, rdx, rsi, rdi, rsp, rbp;
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uint64_t r8, r9, r10, r11, r12, r13, r14, r15;
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uint64_t rip, rflags;
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QEMUCPUSegment cs, ds, es, fs, gs, ss;
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QEMUCPUSegment ldt, tr, gdt, idt;
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uint64_t cr[5];
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};
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typedef struct QEMUCPUState QEMUCPUState;
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static void copy_segment(QEMUCPUSegment *d, SegmentCache *s)
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{
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d->pad = 0;
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d->selector = s->selector;
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d->limit = s->limit;
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d->flags = s->flags;
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d->base = s->base;
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}
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static void qemu_get_cpustate(QEMUCPUState *s, CPUArchState *env)
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{
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memset(s, 0, sizeof(QEMUCPUState));
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||||
|
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s->version = QEMUCPUSTATE_VERSION;
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s->size = sizeof(QEMUCPUState);
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||||
|
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s->rax = env->regs[R_EAX];
|
||||
s->rbx = env->regs[R_EBX];
|
||||
s->rcx = env->regs[R_ECX];
|
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s->rdx = env->regs[R_EDX];
|
||||
s->rsi = env->regs[R_ESI];
|
||||
s->rdi = env->regs[R_EDI];
|
||||
s->rsp = env->regs[R_ESP];
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s->rbp = env->regs[R_EBP];
|
||||
#ifdef TARGET_X86_64
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s->r8 = env->regs[8];
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||||
s->r9 = env->regs[9];
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s->r10 = env->regs[10];
|
||||
s->r11 = env->regs[11];
|
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s->r12 = env->regs[12];
|
||||
s->r13 = env->regs[13];
|
||||
s->r14 = env->regs[14];
|
||||
s->r15 = env->regs[15];
|
||||
#endif
|
||||
s->rip = env->eip;
|
||||
s->rflags = env->eflags;
|
||||
|
||||
copy_segment(&s->cs, &env->segs[R_CS]);
|
||||
copy_segment(&s->ds, &env->segs[R_DS]);
|
||||
copy_segment(&s->es, &env->segs[R_ES]);
|
||||
copy_segment(&s->fs, &env->segs[R_FS]);
|
||||
copy_segment(&s->gs, &env->segs[R_GS]);
|
||||
copy_segment(&s->ss, &env->segs[R_SS]);
|
||||
copy_segment(&s->ldt, &env->ldt);
|
||||
copy_segment(&s->tr, &env->tr);
|
||||
copy_segment(&s->gdt, &env->gdt);
|
||||
copy_segment(&s->idt, &env->idt);
|
||||
|
||||
s->cr[0] = env->cr[0];
|
||||
s->cr[1] = env->cr[1];
|
||||
s->cr[2] = env->cr[2];
|
||||
s->cr[3] = env->cr[3];
|
||||
s->cr[4] = env->cr[4];
|
||||
}
|
||||
|
||||
static inline int cpu_write_qemu_note(write_core_dump_function f,
|
||||
CPUArchState *env,
|
||||
void *opaque,
|
||||
int type)
|
||||
{
|
||||
QEMUCPUState state;
|
||||
Elf64_Nhdr *note64;
|
||||
Elf32_Nhdr *note32;
|
||||
void *note;
|
||||
char *buf;
|
||||
int descsz, note_size, name_size = 5, note_head_size;
|
||||
const char *name = "QEMU";
|
||||
int ret;
|
||||
|
||||
qemu_get_cpustate(&state, env);
|
||||
|
||||
descsz = sizeof(state);
|
||||
if (type == 0) {
|
||||
note_head_size = sizeof(Elf32_Nhdr);
|
||||
} else {
|
||||
note_head_size = sizeof(Elf64_Nhdr);
|
||||
}
|
||||
note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
|
||||
(descsz + 3) / 4) * 4;
|
||||
note = g_malloc(note_size);
|
||||
|
||||
memset(note, 0, note_size);
|
||||
if (type == 0) {
|
||||
note32 = note;
|
||||
note32->n_namesz = cpu_to_le32(name_size);
|
||||
note32->n_descsz = cpu_to_le32(descsz);
|
||||
note32->n_type = 0;
|
||||
} else {
|
||||
note64 = note;
|
||||
note64->n_namesz = cpu_to_le32(name_size);
|
||||
note64->n_descsz = cpu_to_le32(descsz);
|
||||
note64->n_type = 0;
|
||||
}
|
||||
buf = note;
|
||||
buf += ((note_head_size + 3) / 4) * 4;
|
||||
memcpy(buf, name, name_size);
|
||||
buf += ((name_size + 3) / 4) * 4;
|
||||
memcpy(buf, &state, sizeof(state));
|
||||
|
||||
ret = f(note, note_size, opaque);
|
||||
g_free(note);
|
||||
if (ret < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cpu_write_elf64_qemunote(write_core_dump_function f, CPUArchState *env,
|
||||
void *opaque)
|
||||
{
|
||||
return cpu_write_qemu_note(f, env, opaque, 1);
|
||||
}
|
||||
|
||||
int cpu_write_elf32_qemunote(write_core_dump_function f, CPUArchState *env,
|
||||
void *opaque)
|
||||
{
|
||||
return cpu_write_qemu_note(f, env, opaque, 0);
|
||||
}
|
||||
|
||||
int cpu_get_dump_info(ArchDumpInfo *info)
|
||||
{
|
||||
bool lma = false;
|
||||
RAMBlock *block;
|
||||
|
||||
#ifdef TARGET_X86_64
|
||||
lma = !!(first_cpu->hflags & HF_LMA_MASK);
|
||||
#endif
|
||||
|
||||
if (lma) {
|
||||
info->d_machine = EM_X86_64;
|
||||
} else {
|
||||
info->d_machine = EM_386;
|
||||
}
|
||||
info->d_endian = ELFDATA2LSB;
|
||||
|
||||
if (lma) {
|
||||
info->d_class = ELFCLASS64;
|
||||
} else {
|
||||
info->d_class = ELFCLASS32;
|
||||
|
||||
QLIST_FOREACH(block, &ram_list.blocks, next) {
|
||||
if (block->offset + block->length > UINT_MAX) {
|
||||
/* The memory size is greater than 4G */
|
||||
info->d_class = ELFCLASS64;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t cpu_get_note_size(int class, int machine, int nr_cpus)
|
||||
{
|
||||
int name_size = 5; /* "CORE" or "QEMU" */
|
||||
size_t elf_note_size = 0;
|
||||
size_t qemu_note_size = 0;
|
||||
int elf_desc_size = 0;
|
||||
int qemu_desc_size = 0;
|
||||
int note_head_size;
|
||||
|
||||
if (class == ELFCLASS32) {
|
||||
note_head_size = sizeof(Elf32_Nhdr);
|
||||
} else {
|
||||
note_head_size = sizeof(Elf64_Nhdr);
|
||||
}
|
||||
|
||||
if (machine == EM_386) {
|
||||
elf_desc_size = sizeof(x86_elf_prstatus);
|
||||
}
|
||||
#ifdef TARGET_X86_64
|
||||
else {
|
||||
elf_desc_size = sizeof(x86_64_elf_prstatus);
|
||||
}
|
||||
#endif
|
||||
qemu_desc_size = sizeof(QEMUCPUState);
|
||||
|
||||
elf_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
|
||||
(elf_desc_size + 3) / 4) * 4;
|
||||
qemu_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
|
||||
(qemu_desc_size + 3) / 4) * 4;
|
||||
|
||||
return (elf_note_size + qemu_note_size) * nr_cpus;
|
||||
}
|
||||
271
target-i386/arch_memory_mapping.c
Normal file
271
target-i386/arch_memory_mapping.c
Normal file
|
|
@ -0,0 +1,271 @@
|
|||
/*
|
||||
* i386 memory mapping
|
||||
*
|
||||
* Copyright Fujitsu, Corp. 2011, 2012
|
||||
*
|
||||
* Authors:
|
||||
* Wen Congyang <wency@cn.fujitsu.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2. See
|
||||
* the COPYING file in the top-level directory.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "cpu-all.h"
|
||||
|
||||
/* PAE Paging or IA-32e Paging */
|
||||
static void walk_pte(MemoryMappingList *list, target_phys_addr_t pte_start_addr,
|
||||
int32_t a20_mask, target_ulong start_line_addr)
|
||||
{
|
||||
target_phys_addr_t pte_addr, start_paddr;
|
||||
uint64_t pte;
|
||||
target_ulong start_vaddr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 512; i++) {
|
||||
pte_addr = (pte_start_addr + i * 8) & a20_mask;
|
||||
pte = ldq_phys(pte_addr);
|
||||
if (!(pte & PG_PRESENT_MASK)) {
|
||||
/* not present */
|
||||
continue;
|
||||
}
|
||||
|
||||
start_paddr = (pte & ~0xfff) & ~(0x1ULL << 63);
|
||||
if (cpu_physical_memory_is_io(start_paddr)) {
|
||||
/* I/O region */
|
||||
continue;
|
||||
}
|
||||
|
||||
start_vaddr = start_line_addr | ((i & 0x1fff) << 12);
|
||||
memory_mapping_list_add_merge_sorted(list, start_paddr,
|
||||
start_vaddr, 1 << 12);
|
||||
}
|
||||
}
|
||||
|
||||
/* 32-bit Paging */
|
||||
static void walk_pte2(MemoryMappingList *list,
|
||||
target_phys_addr_t pte_start_addr, int32_t a20_mask,
|
||||
target_ulong start_line_addr)
|
||||
{
|
||||
target_phys_addr_t pte_addr, start_paddr;
|
||||
uint32_t pte;
|
||||
target_ulong start_vaddr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 1024; i++) {
|
||||
pte_addr = (pte_start_addr + i * 4) & a20_mask;
|
||||
pte = ldl_phys(pte_addr);
|
||||
if (!(pte & PG_PRESENT_MASK)) {
|
||||
/* not present */
|
||||
continue;
|
||||
}
|
||||
|
||||
start_paddr = pte & ~0xfff;
|
||||
if (cpu_physical_memory_is_io(start_paddr)) {
|
||||
/* I/O region */
|
||||
continue;
|
||||
}
|
||||
|
||||
start_vaddr = start_line_addr | ((i & 0x3ff) << 12);
|
||||
memory_mapping_list_add_merge_sorted(list, start_paddr,
|
||||
start_vaddr, 1 << 12);
|
||||
}
|
||||
}
|
||||
|
||||
/* PAE Paging or IA-32e Paging */
|
||||
static void walk_pde(MemoryMappingList *list, target_phys_addr_t pde_start_addr,
|
||||
int32_t a20_mask, target_ulong start_line_addr)
|
||||
{
|
||||
target_phys_addr_t pde_addr, pte_start_addr, start_paddr;
|
||||
uint64_t pde;
|
||||
target_ulong line_addr, start_vaddr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 512; i++) {
|
||||
pde_addr = (pde_start_addr + i * 8) & a20_mask;
|
||||
pde = ldq_phys(pde_addr);
|
||||
if (!(pde & PG_PRESENT_MASK)) {
|
||||
/* not present */
|
||||
continue;
|
||||
}
|
||||
|
||||
line_addr = start_line_addr | ((i & 0x1ff) << 21);
|
||||
if (pde & PG_PSE_MASK) {
|
||||
/* 2 MB page */
|
||||
start_paddr = (pde & ~0x1fffff) & ~(0x1ULL << 63);
|
||||
if (cpu_physical_memory_is_io(start_paddr)) {
|
||||
/* I/O region */
|
||||
continue;
|
||||
}
|
||||
start_vaddr = line_addr;
|
||||
memory_mapping_list_add_merge_sorted(list, start_paddr,
|
||||
start_vaddr, 1 << 21);
|
||||
continue;
|
||||
}
|
||||
|
||||
pte_start_addr = (pde & ~0xfff) & a20_mask;
|
||||
walk_pte(list, pte_start_addr, a20_mask, line_addr);
|
||||
}
|
||||
}
|
||||
|
||||
/* 32-bit Paging */
|
||||
static void walk_pde2(MemoryMappingList *list,
|
||||
target_phys_addr_t pde_start_addr, int32_t a20_mask,
|
||||
bool pse)
|
||||
{
|
||||
target_phys_addr_t pde_addr, pte_start_addr, start_paddr;
|
||||
uint32_t pde;
|
||||
target_ulong line_addr, start_vaddr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 1024; i++) {
|
||||
pde_addr = (pde_start_addr + i * 4) & a20_mask;
|
||||
pde = ldl_phys(pde_addr);
|
||||
if (!(pde & PG_PRESENT_MASK)) {
|
||||
/* not present */
|
||||
continue;
|
||||
}
|
||||
|
||||
line_addr = (((unsigned int)i & 0x3ff) << 22);
|
||||
if ((pde & PG_PSE_MASK) && pse) {
|
||||
/* 4 MB page */
|
||||
start_paddr = (pde & ~0x3fffff) | ((pde & 0x1fe000) << 19);
|
||||
if (cpu_physical_memory_is_io(start_paddr)) {
|
||||
/* I/O region */
|
||||
continue;
|
||||
}
|
||||
start_vaddr = line_addr;
|
||||
memory_mapping_list_add_merge_sorted(list, start_paddr,
|
||||
start_vaddr, 1 << 22);
|
||||
continue;
|
||||
}
|
||||
|
||||
pte_start_addr = (pde & ~0xfff) & a20_mask;
|
||||
walk_pte2(list, pte_start_addr, a20_mask, line_addr);
|
||||
}
|
||||
}
|
||||
|
||||
/* PAE Paging */
|
||||
static void walk_pdpe2(MemoryMappingList *list,
|
||||
target_phys_addr_t pdpe_start_addr, int32_t a20_mask)
|
||||
{
|
||||
target_phys_addr_t pdpe_addr, pde_start_addr;
|
||||
uint64_t pdpe;
|
||||
target_ulong line_addr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
|
||||
pdpe = ldq_phys(pdpe_addr);
|
||||
if (!(pdpe & PG_PRESENT_MASK)) {
|
||||
/* not present */
|
||||
continue;
|
||||
}
|
||||
|
||||
line_addr = (((unsigned int)i & 0x3) << 30);
|
||||
pde_start_addr = (pdpe & ~0xfff) & a20_mask;
|
||||
walk_pde(list, pde_start_addr, a20_mask, line_addr);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef TARGET_X86_64
|
||||
/* IA-32e Paging */
|
||||
static void walk_pdpe(MemoryMappingList *list,
|
||||
target_phys_addr_t pdpe_start_addr, int32_t a20_mask,
|
||||
target_ulong start_line_addr)
|
||||
{
|
||||
target_phys_addr_t pdpe_addr, pde_start_addr, start_paddr;
|
||||
uint64_t pdpe;
|
||||
target_ulong line_addr, start_vaddr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 512; i++) {
|
||||
pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
|
||||
pdpe = ldq_phys(pdpe_addr);
|
||||
if (!(pdpe & PG_PRESENT_MASK)) {
|
||||
/* not present */
|
||||
continue;
|
||||
}
|
||||
|
||||
line_addr = start_line_addr | ((i & 0x1ffULL) << 30);
|
||||
if (pdpe & PG_PSE_MASK) {
|
||||
/* 1 GB page */
|
||||
start_paddr = (pdpe & ~0x3fffffff) & ~(0x1ULL << 63);
|
||||
if (cpu_physical_memory_is_io(start_paddr)) {
|
||||
/* I/O region */
|
||||
continue;
|
||||
}
|
||||
start_vaddr = line_addr;
|
||||
memory_mapping_list_add_merge_sorted(list, start_paddr,
|
||||
start_vaddr, 1 << 30);
|
||||
continue;
|
||||
}
|
||||
|
||||
pde_start_addr = (pdpe & ~0xfff) & a20_mask;
|
||||
walk_pde(list, pde_start_addr, a20_mask, line_addr);
|
||||
}
|
||||
}
|
||||
|
||||
/* IA-32e Paging */
|
||||
static void walk_pml4e(MemoryMappingList *list,
|
||||
target_phys_addr_t pml4e_start_addr, int32_t a20_mask)
|
||||
{
|
||||
target_phys_addr_t pml4e_addr, pdpe_start_addr;
|
||||
uint64_t pml4e;
|
||||
target_ulong line_addr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 512; i++) {
|
||||
pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
|
||||
pml4e = ldq_phys(pml4e_addr);
|
||||
if (!(pml4e & PG_PRESENT_MASK)) {
|
||||
/* not present */
|
||||
continue;
|
||||
}
|
||||
|
||||
line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48);
|
||||
pdpe_start_addr = (pml4e & ~0xfff) & a20_mask;
|
||||
walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env)
|
||||
{
|
||||
if (!cpu_paging_enabled(env)) {
|
||||
/* paging is disabled */
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (env->cr[4] & CR4_PAE_MASK) {
|
||||
#ifdef TARGET_X86_64
|
||||
if (env->hflags & HF_LMA_MASK) {
|
||||
target_phys_addr_t pml4e_addr;
|
||||
|
||||
pml4e_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
|
||||
walk_pml4e(list, pml4e_addr, env->a20_mask);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
target_phys_addr_t pdpe_addr;
|
||||
|
||||
pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
|
||||
walk_pdpe2(list, pdpe_addr, env->a20_mask);
|
||||
}
|
||||
} else {
|
||||
target_phys_addr_t pde_addr;
|
||||
bool pse;
|
||||
|
||||
pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
|
||||
pse = !!(env->cr[4] & CR4_PSE_MASK);
|
||||
walk_pde2(list, pde_addr, env->a20_mask, pse);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool cpu_paging_enabled(CPUArchState *env)
|
||||
{
|
||||
return env->cr[0] & CR0_PG_MASK;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue