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target/tricore: Refactor PCXI/ICR register fields

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starting from ISA version 1.6.1 (previously known as 1.6P/E), some
bitfields in PCXI and ICR have changed. We also refactor these
registers using the register fields API.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1453
Message-Id: <20230526061946.54514-5-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-05-26 08:19:44 +02:00
parent 0e45f7beca
commit 343cdf2c9a
4 changed files with 123 additions and 56 deletions
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10
target/tricore/translate.c
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@ -75,6 +75,7 @@ typedef struct DisasContext {
int mem_idx;
uint32_t hflags, saved_hflags;
uint64_t features;
uint32_t icr_ie_mask;
} DisasContext;
static int has_feature(DisasContext *ctx, int feature)
@ -7850,12 +7851,12 @@ static void decode_sys_interrupts(DisasContext *ctx)
/* raise EXCP_DEBUG */
break;
case OPC2_32_SYS_DISABLE:
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3);
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
break;
case OPC2_32_SYS_DSYNC:
break;
case OPC2_32_SYS_ENABLE:
tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3);
tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
break;
case OPC2_32_SYS_ISYNC:
break;
@ -8259,6 +8260,11 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
ctx->mem_idx = cpu_mmu_index(env, false);
ctx->hflags = (uint32_t)ctx->base.tb->flags;
ctx->features = env->features;
if (has_feature(ctx, TRICORE_FEATURE_161)) {
ctx->icr_ie_mask = R_ICR_IE_161_MASK;
} else {
ctx->icr_ie_mask = R_ICR_IE_13_MASK;
}
}
static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)