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i386/cpu: Don't enumerate the "invalid" CPU topology level

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In the follow-up change, the CPU topology enumeration will be moved to
QAPI. And considerring "invalid" should not be exposed to QAPI as an
unsettable item, so, as a preparation for future changes, remove
"invalid" level from the current CPU topology enumeration structure
and define it by a macro instead.

Due to the removal of the enumeration of "invalid", bit 0 of
CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid"
level, but will start at the SMT level. Therefore, to honor this change,
update the encoding rule for CPUID[0x1F].

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20241101083331.340178-2-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Zhao Liu 2024-11-01 16:33:23 +08:00 • committed by Philippe Mathieu-Daudé
parent 6e64c8ef8c
commit 34230ce5a9
2 changed files with 10 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

3
include/hw/i386/topology.h
View file

@ -62,6 +62,8 @@ typedef struct X86CPUTopoInfo {
unsigned threads_per_core; unsigned threads_per_core;
} X86CPUTopoInfo; } X86CPUTopoInfo;
#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX
/* /*
* CPUTopoLevel is the general i386 topology hierarchical representation, * CPUTopoLevel is the general i386 topology hierarchical representation,
* ordered by increasing hierarchical relationship. * ordered by increasing hierarchical relationship.
@ -69,7 +71,6 @@ typedef struct X86CPUTopoInfo {
* or AMD (CPUID[0x80000026]). * or AMD (CPUID[0x80000026]).
*/ */
enum CPUTopoLevel { enum CPUTopoLevel {
CPU_TOPO_LEVEL_INVALID,
CPU_TOPO_LEVEL_SMT, CPU_TOPO_LEVEL_SMT,
CPU_TOPO_LEVEL_CORE, CPU_TOPO_LEVEL_CORE,
CPU_TOPO_LEVEL_MODULE, CPU_TOPO_LEVEL_MODULE,

13
target/i386/cpu.c
View file

@ -370,20 +370,21 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
uint32_t *ecx, uint32_t *edx) uint32_t *ecx, uint32_t *edx)
{ {
X86CPU *cpu = env_archcpu(env); X86CPU *cpu = env_archcpu(env);
unsigned long level, next_level; unsigned long level, base_level, next_level;
uint32_t num_threads_next_level, offset_next_level; uint32_t num_threads_next_level, offset_next_level;
assert(count + 1 < CPU_TOPO_LEVEL_MAX); assert(count <= CPU_TOPO_LEVEL_PACKAGE);
/* /*
* Find the No.(count + 1) topology level in avail_cpu_topo bitmap. * Find the No.(count + 1) topology level in avail_cpu_topo bitmap.
* The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT).
*/ */
level = CPU_TOPO_LEVEL_INVALID; level = CPU_TOPO_LEVEL_SMT;
base_level = level;
for (int i = 0; i <= count; i++) { for (int i = 0; i <= count; i++) {
level = find_next_bit(env->avail_cpu_topo, level = find_next_bit(env->avail_cpu_topo,
CPU_TOPO_LEVEL_PACKAGE, CPU_TOPO_LEVEL_PACKAGE,
level + 1); base_level);
/* /*
* CPUID[0x1f] doesn't explicitly encode the package level, * CPUID[0x1f] doesn't explicitly encode the package level,
@ -394,6 +395,8 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
level = CPU_TOPO_LEVEL_INVALID; level = CPU_TOPO_LEVEL_INVALID;
break; break;
} }
/* Search the next level. */
base_level = level + 1;
} }
if (level == CPU_TOPO_LEVEL_INVALID) { if (level == CPU_TOPO_LEVEL_INVALID) {