motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-06 17:23:56 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/arm: Remove log2_esize parameter to gen_mte_checkN

Browse source 
The log2_esize parameter is not used except trivially.
Drop the parameter and the deferral to gen_mte_check1.

This fixes a bug in that the parameters as documented
in the header file were the reverse from those in the
implementation.  Which meant that translate-sve.c was
passing the parameters in the wrong order.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-04-16 11:31:06 -07:00 • committed by Peter Maydell
parent 4c3310c73f
commit 33e74c3172
3 changed files with 10 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

15
target/arm/translate-a64.c
View file

@ -295,9 +295,9 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
* For MTE, check multiple logical sequential accesses. * For MTE, check multiple logical sequential accesses.
*/ */
TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
bool tag_checked, int log2_esize, int total_size) bool tag_checked, int size)
{ {
if (tag_checked && s->mte_active[0] && total_size != (1 << log2_esize)) { if (tag_checked && s->mte_active[0]) {
TCGv_i32 tcg_desc; TCGv_i32 tcg_desc;
TCGv_i64 ret; TCGv_i64 ret;
int desc = 0; int desc = 0;
@ -306,7 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
tcg_desc = tcg_const_i32(desc); tcg_desc = tcg_const_i32(desc);
ret = new_tmp_a64(s); ret = new_tmp_a64(s);
@ -315,7 +315,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
return ret; return ret;
} }
return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize); return clean_data_tbi(s, addr);
} }
typedef struct DisasCompare64 { typedef struct DisasCompare64 {
@ -2965,8 +2965,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
} }
clean_addr = gen_mte_checkN(s, dirty_addr, !is_load, clean_addr = gen_mte_checkN(s, dirty_addr, !is_load,
(wback || rn != 31) && !set_tag, (wback || rn != 31) && !set_tag, 2 << size);
size, 2 << size);
if (is_vector) { if (is_vector) {
if (is_load) { if (is_load) {
@ -3713,7 +3712,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
* promote consecutive little-endian elements below. * promote consecutive little-endian elements below.
*/ */
clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31, clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31,
size, total); total);
/* /*
* Consecutive little-endian elements from a single register * Consecutive little-endian elements from a single register
@ -3866,7 +3865,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
tcg_rn = cpu_reg_sp(s, rn); tcg_rn = cpu_reg_sp(s, rn);
clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
scale, total); total);
tcg_ebytes = tcg_const_i64(1 << scale); tcg_ebytes = tcg_const_i64(1 << scale);
for (xs = 0; xs < selem; xs++) { for (xs = 0; xs < selem; xs++) {

2
target/arm/translate-a64.h
View file

@ -44,7 +44,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
bool tag_checked, int log2_size); bool tag_checked, int log2_size);
TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
bool tag_checked, int count, int log2_esize); bool tag_checked, int size);
/* We should have at some point before trying to access an FP register /* We should have at some point before trying to access an FP register
* done the necessary access check, so assert that * done the necessary access check, so assert that

4
target/arm/translate-sve.c
View file

@ -4264,7 +4264,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
dirty_addr = tcg_temp_new_i64(); dirty_addr = tcg_temp_new_i64();
tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm);
clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8); clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len);
tcg_temp_free_i64(dirty_addr); tcg_temp_free_i64(dirty_addr);
/* /*
@ -4352,7 +4352,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
dirty_addr = tcg_temp_new_i64(); dirty_addr = tcg_temp_new_i64();
tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm);
clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8); clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len);
tcg_temp_free_i64(dirty_addr); tcg_temp_free_i64(dirty_addr);
/* Note that unpredicated load/store of vector/predicate registers /* Note that unpredicated load/store of vector/predicate registers