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target/mips: reimplement SC instruction emulation and use cmpxchg

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Completely rewrite conditional stores handling. Use cmpxchg.

This eliminates need for separate implementations of SC instruction
emulation for user and system emulation.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Leon Alrae 2019-02-11 16:09:23 +01:00 • committed by Aleksandar Markovic
parent c7c7e1e9a5
commit 33a07fa2db
6 changed files with 44 additions and 191 deletions
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6
target/mips/helper.c
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@ -1463,10 +1463,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
{
CPUState *cs = CPU(mips_env_get_cpu(env));
if (exception < EXCP_SC) {
qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
__func__, exception, error_code);
}
qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
__func__, exception, error_code);
cs->exception_index = exception;
env->error_code = error_code;