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target/arm: Improve trans_BFCI

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Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-25 11:19:48 -10:00
parent 8d1b02a6a1
commit 3351889caa
1 changed files with 6 additions and 8 deletions
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14
target/arm/tcg/translate.c
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@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
static bool trans_BFCI(DisasContext *s, arg_BFCI *a) static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
{ {
TCGv_i32 tmp;
int msb = a->msb, lsb = a->lsb; int msb = a->msb, lsb = a->lsb;
TCGv_i32 t_in, t_rd;
int width; int width;
if (!ENABLE_ARCH_6T2) { if (!ENABLE_ARCH_6T2) {
@ -7277,16 +7277,14 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
width = msb + 1 - lsb; width = msb + 1 - lsb;
if (a->rn == 15) { if (a->rn == 15) {
/* BFC */ /* BFC */
tmp = tcg_const_i32(0); t_in = tcg_constant_i32(0);
} else { } else {
/* BFI */ /* BFI */
tmp = load_reg(s, a->rn); t_in = load_reg(s, a->rn);
} }
if (width != 32) { t_rd = load_reg(s, a->rd);
TCGv_i32 tmp2 = load_reg(s, a->rd); tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); store_reg(s, a->rd, t_rd);
}
store_reg(s, a->rd, tmp);
return true; return true;
} }