mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 00:33:55 -06:00
target/cris: Convert to TranslatorOps
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
06188c8981
commit
330ca14bce
1 changed files with 174 additions and 143 deletions
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@ -3114,17 +3114,12 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
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*
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*
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*/
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*/
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/* generate intermediate code for basic block 'tb'. */
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static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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{
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUCRISState *env = cs->env_ptr;
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CPUCRISState *env = cs->env_ptr;
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uint32_t tb_flags = dc->base.tb->flags;
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uint32_t pc_start;
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uint32_t pc_start;
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unsigned int insn_len;
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struct DisasContext ctx;
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struct DisasContext *dc = &ctx;
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uint32_t page_start;
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target_ulong npc;
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int num_insns;
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if (env->pregs[PR_VR] == 32) {
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if (env->pregs[PR_VR] == 32) {
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dc->decoder = crisv32_decoder;
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dc->decoder = crisv32_decoder;
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@ -3134,150 +3129,174 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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dc->clear_locked_irq = 1;
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dc->clear_locked_irq = 1;
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}
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}
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/* Odd PC indicates that branch is rexecuting due to exception in the
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/*
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* Odd PC indicates that branch is rexecuting due to exception in the
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* delayslot, like in real hw.
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* delayslot, like in real hw.
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*/
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*/
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pc_start = tb->pc & ~1;
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pc_start = dc->base.pc_first & ~1;
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dc->base.tb = tb;
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dc->base.pc_first = pc_start;
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dc->base.pc_first = pc_start;
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dc->base.pc_next = pc_start;
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dc->base.pc_next = pc_start;
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dc->base.is_jmp = DISAS_NEXT;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->cpu = env_archcpu(env);
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dc->cpu = env_archcpu(env);
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dc->ppc = pc_start;
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dc->ppc = pc_start;
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dc->pc = pc_start;
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dc->pc = pc_start;
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dc->flags_uptodate = 1;
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dc->flags_uptodate = 1;
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dc->flagx_known = 1;
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dc->flagx_known = 1;
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dc->flags_x = tb->flags & X_FLAG;
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dc->flags_x = tb_flags & X_FLAG;
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dc->cc_x_uptodate = 0;
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dc->cc_x_uptodate = 0;
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dc->cc_mask = 0;
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dc->cc_mask = 0;
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dc->update_cc = 0;
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dc->update_cc = 0;
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dc->clear_prefix = 0;
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dc->clear_prefix = 0;
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dc->cpustate_changed = 0;
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cris_update_cc_op(dc, CC_OP_FLAGS, 4);
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cris_update_cc_op(dc, CC_OP_FLAGS, 4);
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dc->cc_size_uptodate = -1;
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dc->cc_size_uptodate = -1;
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/* Decode TB flags. */
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/* Decode TB flags. */
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dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
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dc->tb_flags = tb_flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG | PFIX_FLAG);
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| X_FLAG | PFIX_FLAG);
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dc->delayed_branch = !!(tb_flags & 7);
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dc->delayed_branch = !!(tb->flags & 7);
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if (dc->delayed_branch) {
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if (dc->delayed_branch) {
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dc->jmp = JMP_INDIRECT;
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dc->jmp = JMP_INDIRECT;
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} else {
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} else {
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dc->jmp = JMP_NOJMP;
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dc->jmp = JMP_NOJMP;
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}
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}
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}
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dc->cpustate_changed = 0;
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static void cris_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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{
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}
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page_start = pc_start & TARGET_PAGE_MASK;
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static void cris_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
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num_insns = 0;
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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gen_tb_start(tb);
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tcg_gen_insn_start(dc->delayed_branch == 1 ? dc->ppc | 1 : dc->pc);
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do {
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}
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tcg_gen_insn_start(dc->delayed_branch == 1
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? dc->ppc | 1 : dc->pc);
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num_insns++;
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if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
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static bool cris_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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const CPUBreakpoint *bp)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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cris_evaluate_flags(dc);
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tcg_gen_movi_tl(env_pc, dc->pc);
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t_gen_raise_exception(EXCP_DEBUG);
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dc->base.is_jmp = DISAS_NORETURN;
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/*
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* The address covered by the breakpoint must be included in
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* [tb->pc, tb->pc + tb->size) in order to for it to be
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* properly cleared -- thus we increment the PC here so that
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* the logic setting tb->size below does the right thing.
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*/
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dc->pc += 2;
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return true;
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}
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static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUCRISState *env = cs->env_ptr;
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unsigned int insn_len;
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/* Pretty disas. */
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LOG_DIS("%8.8x:\t", dc->pc);
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dc->clear_x = 1;
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insn_len = dc->decoder(env, dc);
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dc->ppc = dc->pc;
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dc->pc += insn_len;
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dc->base.pc_next += insn_len;
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if (dc->base.is_jmp == DISAS_NORETURN) {
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return;
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}
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if (dc->clear_x) {
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cris_clear_x_flag(dc);
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}
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/*
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* Check for delayed branches here. If we do it before
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* actually generating any host code, the simulator will just
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* loop doing nothing for on this program location.
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*/
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if (dc->delayed_branch && --dc->delayed_branch == 0) {
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if (dc->base.tb->flags & 7) {
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t_gen_movi_env_TN(dslot, 0);
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}
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if (dc->cpustate_changed
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|| !dc->flagx_known
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|| (dc->flags_x != (dc->base.tb->flags & X_FLAG))) {
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cris_store_direct_jmp(dc);
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}
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if (dc->clear_locked_irq) {
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dc->clear_locked_irq = 0;
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t_gen_movi_env_TN(locked_irq, 0);
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}
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if (dc->jmp == JMP_DIRECT_CC) {
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TCGLabel *l1 = gen_new_label();
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cris_evaluate_flags(dc);
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cris_evaluate_flags(dc);
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tcg_gen_movi_tl(env_pc, dc->pc);
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t_gen_raise_exception(EXCP_DEBUG);
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/* Conditional jmp. */
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tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
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gen_goto_tb(dc, 1, dc->jmp_pc);
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gen_set_label(l1);
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gen_goto_tb(dc, 0, dc->pc);
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dc->base.is_jmp = DISAS_NORETURN;
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dc->base.is_jmp = DISAS_NORETURN;
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/* The address covered by the breakpoint must be included in
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dc->jmp = JMP_NOJMP;
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[tb->pc, tb->pc + tb->size) in order to for it to be
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} else if (dc->jmp == JMP_DIRECT) {
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properly cleared -- thus we increment the PC here so that
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cris_evaluate_flags(dc);
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the logic setting tb->size below does the right thing. */
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gen_goto_tb(dc, 0, dc->jmp_pc);
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dc->pc += 2;
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dc->base.is_jmp = DISAS_NORETURN;
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break;
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dc->jmp = JMP_NOJMP;
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} else {
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TCGv c = tcg_const_tl(dc->pc);
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t_gen_cc_jmp(env_btarget, c);
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tcg_temp_free(c);
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dc->base.is_jmp = DISAS_JUMP;
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}
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}
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}
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/* Pretty disas. */
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/* Force an update if the per-tb cpu state has changed. */
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LOG_DIS("%8.8x:\t", dc->pc);
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if (dc->base.is_jmp == DISAS_NEXT
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&& (dc->cpustate_changed
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|| !dc->flagx_known
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|| (dc->flags_x != (dc->base.tb->flags & X_FLAG)))) {
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dc->base.is_jmp = DISAS_UPDATE;
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tcg_gen_movi_tl(env_pc, dc->pc);
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}
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if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
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/*
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gen_io_start();
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* FIXME: Only the first insn in the TB should cross a page boundary.
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}
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* If we can detect the length of the next insn easily, we should.
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dc->clear_x = 1;
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* In the meantime, simply stop when we do cross.
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*/
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if (dc->base.is_jmp == DISAS_NEXT
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&& ((dc->pc ^ dc->base.pc_first) & TARGET_PAGE_MASK) != 0) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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}
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}
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insn_len = dc->decoder(env, dc);
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static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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dc->ppc = dc->pc;
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{
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dc->pc += insn_len;
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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if (dc->clear_x) {
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DisasJumpType is_jmp = dc->base.is_jmp;
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cris_clear_x_flag(dc);
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target_ulong npc = dc->pc;
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}
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/* Check for delayed branches here. If we do it before
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if (is_jmp == DISAS_NORETURN) {
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actually generating any host code, the simulator will just
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/* If we have a broken branch+delayslot sequence, it's too late. */
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loop doing nothing for on this program location. */
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assert(dc->delayed_branch != 1);
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if (dc->delayed_branch) {
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return;
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dc->delayed_branch--;
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}
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if (dc->delayed_branch == 0) {
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if (tb->flags & 7) {
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t_gen_movi_env_TN(dslot, 0);
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}
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if (dc->cpustate_changed || !dc->flagx_known
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|| (dc->flags_x != (tb->flags & X_FLAG))) {
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cris_store_direct_jmp(dc);
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}
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if (dc->clear_locked_irq) {
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dc->clear_locked_irq = 0;
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t_gen_movi_env_TN(locked_irq, 0);
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}
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if (dc->jmp == JMP_DIRECT_CC) {
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TCGLabel *l1 = gen_new_label();
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cris_evaluate_flags(dc);
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/* Conditional jmp. */
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tcg_gen_brcondi_tl(TCG_COND_EQ,
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env_btaken, 0, l1);
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gen_goto_tb(dc, 1, dc->jmp_pc);
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gen_set_label(l1);
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gen_goto_tb(dc, 0, dc->pc);
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dc->base.is_jmp = DISAS_NORETURN;
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dc->jmp = JMP_NOJMP;
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} else if (dc->jmp == JMP_DIRECT) {
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cris_evaluate_flags(dc);
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gen_goto_tb(dc, 0, dc->jmp_pc);
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dc->base.is_jmp = DISAS_NORETURN;
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dc->jmp = JMP_NOJMP;
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} else {
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TCGv c = tcg_const_tl(dc->pc);
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t_gen_cc_jmp(env_btarget, c);
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tcg_temp_free(c);
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dc->base.is_jmp = DISAS_JUMP;
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}
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break;
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}
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}
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/* If we are rexecuting a branch due to exceptions on
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delay slots don't break. */
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if (!(tb->pc & 1) && cs->singlestep_enabled) {
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break;
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}
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} while (!dc->base.is_jmp && !dc->cpustate_changed
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&& !tcg_op_buf_full()
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&& !singlestep
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&& (dc->pc - page_start < TARGET_PAGE_SIZE)
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&& num_insns < max_insns);
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if (dc->clear_locked_irq) {
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if (dc->clear_locked_irq) {
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t_gen_movi_env_TN(locked_irq, 0);
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t_gen_movi_env_TN(locked_irq, 0);
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}
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}
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npc = dc->pc;
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/* Force an update if the per-tb cpu state has changed. */
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if (dc->base.is_jmp == DISAS_NEXT
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&& (dc->cpustate_changed || !dc->flagx_known
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|| (dc->flags_x != (tb->flags & X_FLAG)))) {
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dc->base.is_jmp = DISAS_UPDATE;
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tcg_gen_movi_tl(env_pc, npc);
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}
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/* Broken branch+delayslot sequence. */
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/* Broken branch+delayslot sequence. */
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if (dc->delayed_branch == 1) {
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if (dc->delayed_branch == 1) {
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/* Set env->dslot to the size of the branch insn. */
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/* Set env->dslot to the size of the branch insn. */
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@ -3287,45 +3306,57 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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cris_evaluate_flags(dc);
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cris_evaluate_flags(dc);
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if (unlikely(cs->singlestep_enabled)) {
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if (unlikely(dc->base.singlestep_enabled)) {
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if (dc->base.is_jmp == DISAS_NEXT) {
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switch (is_jmp) {
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case DISAS_TOO_MANY:
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tcg_gen_movi_tl(env_pc, npc);
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tcg_gen_movi_tl(env_pc, npc);
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}
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/* fall through */
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t_gen_raise_exception(EXCP_DEBUG);
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} else {
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switch (dc->base.is_jmp) {
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case DISAS_NEXT:
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gen_goto_tb(dc, 1, npc);
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break;
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default:
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case DISAS_JUMP:
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case DISAS_JUMP:
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case DISAS_UPDATE:
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case DISAS_UPDATE:
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/* indicate that the hash table must be used
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t_gen_raise_exception(EXCP_DEBUG);
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to find the next TB */
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return;
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tcg_gen_exit_tb(NULL, 0);
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default:
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break;
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case DISAS_NORETURN:
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/* nothing more to generate */
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break;
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break;
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}
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}
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g_assert_not_reached();
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}
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}
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gen_tb_end(tb, num_insns);
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tb->size = dc->pc - pc_start;
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switch (is_jmp) {
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tb->icount = num_insns;
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case DISAS_TOO_MANY:
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gen_goto_tb(dc, 0, npc);
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#ifdef DEBUG_DISAS
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break;
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#if !DISAS_CRIS
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case DISAS_JUMP:
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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case DISAS_UPDATE:
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&& qemu_log_in_addr_range(pc_start)) {
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/* Indicate that interupts must be re-evaluated before the next TB. */
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FILE *logfile = qemu_log_lock();
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tcg_gen_exit_tb(NULL, 0);
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qemu_log("--------------\n");
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break;
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qemu_log("IN: %s\n", lookup_symbol(pc_start));
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default:
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log_target_disas(cs, pc_start, dc->pc - pc_start);
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g_assert_not_reached();
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qemu_log_unlock(logfile);
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}
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}
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#endif
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}
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||||||
#endif
|
|
||||||
|
static void cris_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
|
||||||
|
{
|
||||||
|
if (!DISAS_CRIS) {
|
||||||
|
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
|
||||||
|
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static const TranslatorOps cris_tr_ops = {
|
||||||
|
.init_disas_context = cris_tr_init_disas_context,
|
||||||
|
.tb_start = cris_tr_tb_start,
|
||||||
|
.insn_start = cris_tr_insn_start,
|
||||||
|
.breakpoint_check = cris_tr_breakpoint_check,
|
||||||
|
.translate_insn = cris_tr_translate_insn,
|
||||||
|
.tb_stop = cris_tr_tb_stop,
|
||||||
|
.disas_log = cris_tr_disas_log,
|
||||||
|
};
|
||||||
|
|
||||||
|
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
|
||||||
|
{
|
||||||
|
DisasContext dc;
|
||||||
|
translator_loop(&cris_tr_ops, &dc.base, cs, tb, max_insns);
|
||||||
}
|
}
|
||||||
|
|
||||||
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue