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target/riscv: rvv-1.0: Add Zve32f extension into RISC-V

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Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-01-18 09:45:14 +08:00 • committed by Alistair Francis
parent bfefe406b7
commit 32e579b8c5
5 changed files with 7 additions and 4 deletions
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2
target/riscv/csr.c
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@ -51,7 +51,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
if (env->misa_ext & RVV ||
cpu->cfg.ext_zve64f) {
cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;