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RISC-V: Adding XTheadCondMov ISA extension

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This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:05 +01:00 • committed by Alistair Francis
parent fa13458546
commit 3290933853
5 changed files with 43 additions and 1 deletions
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35
target/riscv/insn_trans/trans_xthead.c.inc
View file

@ -40,6 +40,12 @@
} \
} while (0)
#define REQUIRE_XTHEADCONDMOV(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadcondmov) { \
return false; \
} \
} while (0)
#define REQUIRE_XTHEADSYNC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadsync) { \
return false; \
@ -264,6 +270,35 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
/* XTheadCondMov */
static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond)
{
TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
TCGv old = get_gpr(ctx, a->rd, EXT_NONE);
TCGv dest = dest_gpr(ctx, a->rd);
tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
/* th.mveqz: "if (rs2 == 0) rd = rs1;" */
static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a)
{
REQUIRE_XTHEADCONDMOV(ctx);
return gen_th_condmove(ctx, a, TCG_COND_EQ);
}
/* th.mvnez: "if (rs2 != 0) rd = rs1;" */
static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
{
REQUIRE_XTHEADCONDMOV(ctx);
return gen_th_condmove(ctx, a, TCG_COND_NE);
}
/* XTheadSync */
static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)