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amd_iommu: report x2APIC support to the operating system
This commit adds XTSup configuration to let user choose to whether enable this feature or not. When XTSup is enabled, additional bytes in IRTE with enabled guest virtual VAPIC are used to support 32-bit destination id. Additionally, this commit exports IVHD type 0x11 besides the old IVHD type 0x10 in ACPI table. IVHD type 0x10 does not report full set of IOMMU features only the legacy ones, so operating system (e.g. Linux) may only detects x2APIC support if IVHD type 0x11 is available. The IVHD type 0x10 is kept so that old operating system that only parses type 0x10 can detect the IOMMU device. Besides, an amd_iommu-stub.c file is created to provide the definition for amdvi_extended_feature_register when CONFIG_AMD_IOMMU=n. This function is used by acpi-build.c to get the extended feature register value for building the ACPI table. When CONFIG_AMD_IOMMU=y, this function is defined in amd_iommu.c. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-7-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bui Quang Minh
Michael S. Tsirkin
parent
595cd6fd9d
commit
328a11a08a
5 changed files with 134 additions and 47 deletions
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@ -2333,30 +2333,23 @@ static void
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build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
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const char *oem_table_id)
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{
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int ivhd_table_len = 24;
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AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
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GArray *ivhd_blob = g_array_new(false, true, 1);
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AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
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.oem_table_id = oem_table_id };
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uint64_t feature_report;
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acpi_table_begin(&table, table_data);
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/* IVinfo - IO virtualization information common to all
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* IOMMU units in a system
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*/
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build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
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build_append_int_noprefix(table_data,
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(1UL << 0) | /* EFRSup */
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(40UL << 8), /* PASize */
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4);
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/* reserved */
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build_append_int_noprefix(table_data, 0, 8);
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/* IVHD definition - type 10h */
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build_append_int_noprefix(table_data, 0x10, 1);
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/* virtualization flags */
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build_append_int_noprefix(table_data,
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(1UL << 0) | /* HtTunEn */
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(1UL << 4) | /* iotblSup */
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(1UL << 6) | /* PrefSup */
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(1UL << 7), /* PPRSup */
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1);
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/*
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* A PCI bus walk, for each PCI host bridge, is necessary to create a
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* complete set of IVHD entries. Do this into a separate blob so that we
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@ -2376,18 +2369,34 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
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build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
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}
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ivhd_table_len += ivhd_blob->len;
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/*
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* When interrupt remapping is supported, we add a special IVHD device
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* for type IO-APIC.
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* for type IO-APIC
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* Refer to spec - Table 95: IVHD device entry type codes
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*
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* Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
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* See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
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*/
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if (x86_iommu_ir_supported(x86_iommu_get_default())) {
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ivhd_table_len += 8;
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build_append_int_noprefix(ivhd_blob,
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(0x1ull << 56) | /* type IOAPIC */
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(IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
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0x48, /* special device */
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8);
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}
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/* IVHD definition - type 10h */
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build_append_int_noprefix(table_data, 0x10, 1);
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/* virtualization flags */
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build_append_int_noprefix(table_data,
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(1UL << 0) | /* HtTunEn */
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(1UL << 4) | /* iotblSup */
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(1UL << 6) | /* PrefSup */
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(1UL << 7), /* PPRSup */
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1);
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/* IVHD length */
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build_append_int_noprefix(table_data, ivhd_table_len, 2);
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build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2);
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/* DeviceID */
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build_append_int_noprefix(table_data,
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object_property_get_int(OBJECT(&s->pci), "addr",
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@ -2401,31 +2410,53 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
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/* IOMMU info */
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build_append_int_noprefix(table_data, 0, 2);
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/* IOMMU Feature Reporting */
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build_append_int_noprefix(table_data,
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(48UL << 30) | /* HATS */
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(48UL << 28) | /* GATS */
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(1UL << 2) | /* GTSup */
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(1UL << 6), /* GASup */
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4);
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feature_report = (48UL << 30) | /* HATS */
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(48UL << 28) | /* GATS */
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(1UL << 2) | /* GTSup */
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(1UL << 6); /* GASup */
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if (s->xtsup) {
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feature_report |= (1UL << 0); /* XTSup */
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}
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build_append_int_noprefix(table_data, feature_report, 4);
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/* IVHD entries as found above */
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g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
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g_array_free(ivhd_blob, TRUE);
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/*
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* Add a special IVHD device type.
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* Refer to spec - Table 95: IVHD device entry type codes
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*
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* Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
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* See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
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*/
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if (x86_iommu_ir_supported(x86_iommu_get_default())) {
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build_append_int_noprefix(table_data,
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(0x1ull << 56) | /* type IOAPIC */
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(IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
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0x48, /* special device */
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8);
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}
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/* IVHD definition - type 11h */
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build_append_int_noprefix(table_data, 0x11, 1);
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/* virtualization flags */
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build_append_int_noprefix(table_data,
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(1UL << 0) | /* HtTunEn */
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(1UL << 4), /* iotblSup */
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1);
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/* IVHD length */
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build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2);
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/* DeviceID */
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build_append_int_noprefix(table_data,
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object_property_get_int(OBJECT(&s->pci), "addr",
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&error_abort), 2);
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/* Capability offset */
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build_append_int_noprefix(table_data, s->pci.capab_offset, 2);
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/* IOMMU base address */
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build_append_int_noprefix(table_data, s->mmio.addr, 8);
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/* PCI Segment Group */
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build_append_int_noprefix(table_data, 0, 2);
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/* IOMMU info */
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build_append_int_noprefix(table_data, 0, 2);
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/* IOMMU Attributes */
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build_append_int_noprefix(table_data, 0, 4);
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/* EFR Register Image */
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build_append_int_noprefix(table_data,
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amdvi_extended_feature_register(s),
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8);
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/* EFR Register Image 2 */
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build_append_int_noprefix(table_data, 0, 8);
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/* IVHD entries as found above */
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g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
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g_array_free(ivhd_blob, TRUE);
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acpi_table_end(linker, &table);
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}
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