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target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu'

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Follow the naming used by other files in target/i386/.

No functional changes.

Suggested-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231020111136.44401-4-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-10-20 13:03:07 +02:00
parent 5366a0644f
commit 3152e95413
1 changed files with 9 additions and 9 deletions
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18
target/i386/hvf/x86_emu.c
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@ -665,7 +665,7 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
void simulate_rdmsr(CPUX86State *env) void simulate_rdmsr(CPUX86State *env)
{ {
X86CPU *x86_cpu = env_archcpu(env); X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env); uint32_t msr = ECX(env);
uint64_t val = 0; uint64_t val = 0;
@ -675,10 +675,10 @@ void simulate_rdmsr(CPUX86State *env)
val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
break; break;
case MSR_IA32_APICBASE: case MSR_IA32_APICBASE:
val = cpu_get_apic_base(x86_cpu->apic_state); val = cpu_get_apic_base(cpu->apic_state);
break; break;
case MSR_IA32_UCODE_REV: case MSR_IA32_UCODE_REV:
val = x86_cpu->ucode_rev; val = cpu->ucode_rev;
break; break;
case MSR_EFER: case MSR_EFER:
val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
@ -766,7 +766,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
void simulate_wrmsr(CPUX86State *env) void simulate_wrmsr(CPUX86State *env)
{ {
X86CPU *x86_cpu = env_archcpu(env); X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env); uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@ -775,7 +775,7 @@ void simulate_wrmsr(CPUX86State *env)
case MSR_IA32_TSC: case MSR_IA32_TSC:
break; break;
case MSR_IA32_APICBASE: case MSR_IA32_APICBASE:
cpu_set_apic_base(x86_cpu->apic_state, data); cpu_set_apic_base(cpu->apic_state, data);
break; break;
case MSR_FSBASE: case MSR_FSBASE:
wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
@ -1419,8 +1419,8 @@ static void init_cmd_handler()
void load_regs(CPUState *cs) void load_regs(CPUState *cs)
{ {
X86CPU *x86_cpu = X86_CPU(cs); X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &cpu->env;
int i = 0; int i = 0;
RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX); RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
@ -1442,8 +1442,8 @@ void load_regs(CPUState *cs)
void store_regs(CPUState *cs) void store_regs(CPUState *cs)
{ {
X86CPU *x86_cpu = X86_CPU(cs); X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &x86_cpu->env; CPUX86State *env = &cpu->env;
int i = 0; int i = 0;
wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); wreg(cs->accel->fd, HV_X86_RAX, RAX(env));