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arm/cpu: Store id_pfr0/1/2 into the idregs array

Browse source 
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20250617153931.1330449-10-cohuck@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Eric Auger 2025-07-01 15:08:28 +01:00 • committed by Peter Maydell
parent c0c2344c43
commit 30ca689900
10 changed files with 82 additions and 89 deletions
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5
hw/intc/armv7m_nvic.c
View file

@ -988,6 +988,7 @@ static void nvic_nmi_trigger(void *opaque, int n, int level)
static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
{ {
ARMCPU *cpu = s->cpu; ARMCPU *cpu = s->cpu;
ARMISARegisters *isar = &cpu->isar;
uint32_t val; uint32_t val;
switch (offset) { switch (offset) {
@ -1263,12 +1264,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset; goto bad_offset;
} }
return cpu->isar.id_pfr0; return GET_IDREG(isar, ID_PFR0);
case 0xd44: /* PFR1. */ case 0xd44: /* PFR1. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset; goto bad_offset;
} }
return cpu->isar.id_pfr1; return GET_IDREG(isar, ID_PFR1);
case 0xd48: /* DFR0. */ case 0xd48: /* DFR0. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset; goto bad_offset;

10
target/arm/cpu-features.h
View file

@ -137,12 +137,12 @@ static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
{ {
return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; return FIELD_EX32_IDREG(id, ID_PFR0, RAS) != 0;
} }
static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
{ {
return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; return FIELD_EX32_IDREG(id, ID_PFR1, MPROGMOD) != 0;
} }
static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
@ -151,7 +151,7 @@ static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
* Return true if M-profile state handling insns * Return true if M-profile state handling insns
* (VSCCLRM, CLRM, FPCTX access insns) are implemented * (VSCCLRM, CLRM, FPCTX access insns) are implemented
*/ */
return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; return FIELD_EX32_IDREG(id, ID_PFR1, SECURITY) >= 3;
} }
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
@ -350,12 +350,12 @@ static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
{ {
return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; return FIELD_EX32_IDREG(id, ID_PFR0, DIT) != 0;
} }
static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
{ {
return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; return FIELD_EX32_IDREG(id, ID_PFR2, SSBS) != 0;
} }
static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)

8
target/arm/cpu.c
View file

@ -2317,7 +2317,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* Disable the security extension feature bits in the processor * Disable the security extension feature bits in the processor
* feature registers as well. * feature registers as well.
*/ */
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0);
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0);
@ -2357,8 +2357,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* registers if we don't have EL2. * registers if we don't have EL2.
*/ */
FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0);
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0);
ID_PFR1, VIRTUALIZATION, 0);
} }
if (cpu_isar_feature(aa64_mte, cpu)) { if (cpu_isar_feature(aa64_mte, cpu)) {
@ -2421,8 +2420,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
/* FEAT_AMU (Activity Monitors Extension) */ /* FEAT_AMU (Activity Monitors Extension) */
FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0);
cpu->isar.id_pfr0 = FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0);
FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
/* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0);
} }

3
target/arm/cpu.h
View file

@ -1056,9 +1056,6 @@ struct ArchCPU {
uint32_t id_mmfr3; uint32_t id_mmfr3;
uint32_t id_mmfr4; uint32_t id_mmfr4;
uint32_t id_mmfr5; uint32_t id_mmfr5;
uint32_t id_pfr0;
uint32_t id_pfr1;
uint32_t id_pfr2;
uint32_t mvfr0; uint32_t mvfr0;
uint32_t mvfr1; uint32_t mvfr1;
uint32_t mvfr2; uint32_t mvfr2;

8
target/arm/cpu64.c
View file

@ -652,8 +652,8 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004; cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838; cpu->reset_sctlr = 0x00c50838;
cpu->isar.id_pfr0 = 0x00000131; SET_IDREG(isar, ID_PFR0, 0x00000131);
cpu->isar.id_pfr1 = 0x00011011; SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;
@ -714,8 +714,8 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x84448004; /* L1Ip = VIPT */ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->reset_sctlr = 0x00c50838; cpu->reset_sctlr = 0x00c50838;
cpu->isar.id_pfr0 = 0x00000131; SET_IDREG(isar, ID_PFR0, 0x00000131);
cpu->isar.id_pfr1 = 0x00011011; SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;

8
target/arm/helper.c
View file

@ -6932,7 +6932,7 @@ static void define_pmu_regs(ARMCPU *cpu)
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
{ {
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
uint64_t pfr1 = cpu->isar.id_pfr1; uint64_t pfr1 = GET_IDREG(&cpu->isar, ID_PFR1);
if (env->gicv3state) { if (env->gicv3state) {
pfr1 |= 1 << 28; pfr1 |= 1 << 28;
@ -7777,7 +7777,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
.resetvalue = cpu->isar.id_pfr0 }, .resetvalue = GET_IDREG(isar, ID_PFR0)},
/* /*
* ID_PFR1 is not a plain ARM_CP_CONST because we don't know * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
* the value of the GIC field until after we define these regs. * the value of the GIC field until after we define these regs.
@ -7788,7 +7788,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
.type = ARM_CP_CONST, .type = ARM_CP_CONST,
.resetvalue = cpu->isar.id_pfr1, .resetvalue = GET_IDREG(isar, ID_PFR1),
#else #else
.type = ARM_CP_NO_RAW, .type = ARM_CP_NO_RAW,
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
@ -8130,7 +8130,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3, .accessfn = access_aa64_tid3,
.resetvalue = cpu->isar.id_pfr2 }, .resetvalue = GET_IDREG(isar, ID_PFR2)},
{ .name = "ID_DFR1", .state = ARM_CP_STATE_BOTH, { .name = "ID_DFR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,

9
target/arm/kvm.c
View file

@ -332,10 +332,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* than skipping the reads and leaving 0, as we must avoid * than skipping the reads and leaving 0, as we must avoid
* considering the values in every case. * considering the values in every case.
*/ */
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, err |= get_host_cpu_reg(fd, ahcf, ID_PFR0_EL1_IDX);
ARM64_SYS_REG(3, 0, 0, 1, 0)); err |= get_host_cpu_reg(fd, ahcf, ID_PFR1_EL1_IDX);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
ARM64_SYS_REG(3, 0, 0, 1, 1));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
ARM64_SYS_REG(3, 0, 0, 1, 2)); ARM64_SYS_REG(3, 0, 0, 1, 2));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
@ -362,8 +360,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 3, 1)); ARM64_SYS_REG(3, 0, 0, 3, 1));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
ARM64_SYS_REG(3, 0, 0, 3, 2)); ARM64_SYS_REG(3, 0, 0, 3, 2));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, err |= get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX);
ARM64_SYS_REG(3, 0, 0, 3, 4));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
ARM64_SYS_REG(3, 0, 0, 3, 5)); ARM64_SYS_REG(3, 0, 0, 3, 5));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,

24
target/arm/tcg/cpu-v7m.c
View file

@ -59,8 +59,8 @@ static void cortex_m0_initfn(Object *obj)
* by looking at ID register fields. We use the same values as * by looking at ID register fields. We use the same values as
* for the M3. * for the M3.
*/ */
cpu->isar.id_pfr0 = 0x00000030; SET_IDREG(isar, ID_PFR0, 0x00000030);
cpu->isar.id_pfr1 = 0x00000200; SET_IDREG(isar, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030; cpu->isar.id_mmfr0 = 0x00000030;
@ -85,8 +85,8 @@ static void cortex_m3_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
cpu->midr = 0x410fc231; cpu->midr = 0x410fc231;
cpu->pmsav7_dregion = 8; cpu->pmsav7_dregion = 8;
cpu->isar.id_pfr0 = 0x00000030; SET_IDREG(isar, ID_PFR0, 0x00000030);
cpu->isar.id_pfr1 = 0x00000200; SET_IDREG(isar, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030; cpu->isar.id_mmfr0 = 0x00000030;
@ -116,8 +116,8 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110021; cpu->isar.mvfr0 = 0x10110021;
cpu->isar.mvfr1 = 0x11000011; cpu->isar.mvfr1 = 0x11000011;
cpu->isar.mvfr2 = 0x00000000; cpu->isar.mvfr2 = 0x00000000;
cpu->isar.id_pfr0 = 0x00000030; SET_IDREG(isar, ID_PFR0, 0x00000030);
cpu->isar.id_pfr1 = 0x00000200; SET_IDREG(isar, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030; cpu->isar.id_mmfr0 = 0x00000030;
@ -147,8 +147,8 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110221; cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12000011; cpu->isar.mvfr1 = 0x12000011;
cpu->isar.mvfr2 = 0x00000040; cpu->isar.mvfr2 = 0x00000040;
cpu->isar.id_pfr0 = 0x00000030; SET_IDREG(isar, ID_PFR0, 0x00000030);
cpu->isar.id_pfr1 = 0x00000200; SET_IDREG(isar, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00100030; cpu->isar.id_mmfr0 = 0x00100030;
@ -180,8 +180,8 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110021; cpu->isar.mvfr0 = 0x10110021;
cpu->isar.mvfr1 = 0x11000011; cpu->isar.mvfr1 = 0x11000011;
cpu->isar.mvfr2 = 0x00000040; cpu->isar.mvfr2 = 0x00000040;
cpu->isar.id_pfr0 = 0x00000030; SET_IDREG(isar, ID_PFR0, 0x00000030);
cpu->isar.id_pfr1 = 0x00000210; SET_IDREG(isar, ID_PFR1, 0x00000210);
cpu->isar.id_dfr0 = 0x00200000; cpu->isar.id_dfr0 = 0x00200000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00101F40; cpu->isar.id_mmfr0 = 0x00101F40;
@ -218,8 +218,8 @@ static void cortex_m55_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110221; cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12100211; cpu->isar.mvfr1 = 0x12100211;
cpu->isar.mvfr2 = 0x00000040; cpu->isar.mvfr2 = 0x00000040;
cpu->isar.id_pfr0 = 0x20000030; SET_IDREG(isar, ID_PFR0, 0x20000030);
cpu->isar.id_pfr1 = 0x00000230; SET_IDREG(isar, ID_PFR1, 0x00000230);
cpu->isar.id_dfr0 = 0x10200000; cpu->isar.id_dfr0 = 0x10200000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00111040; cpu->isar.id_mmfr0 = 0x00111040;

52
target/arm/tcg/cpu32.c
View file

@ -71,16 +71,16 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
cpu->isar.id_mmfr5 = t; cpu->isar.id_mmfr5 = t;
t = cpu->isar.id_pfr0; t = GET_IDREG(isar, ID_PFR0);
t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
cpu->isar.id_pfr0 = t; SET_IDREG(isar, ID_PFR0, t);
t = cpu->isar.id_pfr2; t = GET_IDREG(isar, ID_PFR2);
t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
cpu->isar.id_pfr2 = t; SET_IDREG(isar, ID_PFR2, t);
t = cpu->isar.id_dfr0; t = cpu->isar.id_dfr0;
t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
@ -228,8 +228,8 @@ static void arm1136_r2_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000; cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2; cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078; cpu->reset_sctlr = 0x00050078;
cpu->isar.id_pfr0 = 0x111; SET_IDREG(isar, ID_PFR0, 0x111);
cpu->isar.id_pfr1 = 0x1; SET_IDREG(isar, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0x2; cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3; cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
@ -260,8 +260,8 @@ static void arm1136_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000; cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2; cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078; cpu->reset_sctlr = 0x00050078;
cpu->isar.id_pfr0 = 0x111; SET_IDREG(isar, ID_PFR0, 0x111);
cpu->isar.id_pfr1 = 0x1; SET_IDREG(isar, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0x2; cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3; cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
@ -293,8 +293,8 @@ static void arm1176_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000; cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2; cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078; cpu->reset_sctlr = 0x00050078;
cpu->isar.id_pfr0 = 0x111; SET_IDREG(isar, ID_PFR0, 0x111);
cpu->isar.id_pfr1 = 0x11; SET_IDREG(isar, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x33; cpu->isar.id_dfr0 = 0x33;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
@ -323,8 +323,8 @@ static void arm11mpcore_initfn(Object *obj)
cpu->isar.mvfr0 = 0x11111111; cpu->isar.mvfr0 = 0x11111111;
cpu->isar.mvfr1 = 0x00000000; cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
cpu->isar.id_pfr0 = 0x111; SET_IDREG(isar, ID_PFR0, 0x111);
cpu->isar.id_pfr1 = 0x1; SET_IDREG(isar, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0; cpu->isar.id_dfr0 = 0;
cpu->id_afr0 = 0x2; cpu->id_afr0 = 0x2;
cpu->isar.id_mmfr0 = 0x01100103; cpu->isar.id_mmfr0 = 0x01100103;
@ -363,8 +363,8 @@ static void cortex_a8_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00011111; cpu->isar.mvfr1 = 0x00011111;
cpu->ctr = 0x82048004; cpu->ctr = 0x82048004;
cpu->reset_sctlr = 0x00c50078; cpu->reset_sctlr = 0x00c50078;
cpu->isar.id_pfr0 = 0x1031; SET_IDREG(isar, ID_PFR0, 0x1031);
cpu->isar.id_pfr1 = 0x11; SET_IDREG(isar, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x400; cpu->isar.id_dfr0 = 0x400;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x31100003; cpu->isar.id_mmfr0 = 0x31100003;
@ -439,8 +439,8 @@ static void cortex_a9_initfn(Object *obj)
cpu->isar.mvfr1 = 0x01111111; cpu->isar.mvfr1 = 0x01111111;
cpu->ctr = 0x80038003; cpu->ctr = 0x80038003;
cpu->reset_sctlr = 0x00c50078; cpu->reset_sctlr = 0x00c50078;
cpu->isar.id_pfr0 = 0x1031; SET_IDREG(isar, ID_PFR0, 0x1031);
cpu->isar.id_pfr1 = 0x11; SET_IDREG(isar, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x000; cpu->isar.id_dfr0 = 0x000;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x00100103; cpu->isar.id_mmfr0 = 0x00100103;
@ -505,8 +505,8 @@ static void cortex_a7_initfn(Object *obj)
cpu->isar.mvfr1 = 0x11111111; cpu->isar.mvfr1 = 0x11111111;
cpu->ctr = 0x84448003; cpu->ctr = 0x84448003;
cpu->reset_sctlr = 0x00c50078; cpu->reset_sctlr = 0x00c50078;
cpu->isar.id_pfr0 = 0x00001131; SET_IDREG(isar, ID_PFR0, 0x00001131);
cpu->isar.id_pfr1 = 0x00011011; SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x02010555; cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;
@ -557,8 +557,8 @@ static void cortex_a15_initfn(Object *obj)
cpu->isar.mvfr1 = 0x11111111; cpu->isar.mvfr1 = 0x11111111;
cpu->ctr = 0x8444c004; cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50078; cpu->reset_sctlr = 0x00c50078;
cpu->isar.id_pfr0 = 0x00001131; SET_IDREG(isar, ID_PFR0, 0x00001131);
cpu->isar.id_pfr1 = 0x00011011; SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x02010555; cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;
@ -601,8 +601,8 @@ static void cortex_r5_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMSA);
set_feature(&cpu->env, ARM_FEATURE_PMU); set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->midr = 0x411fc153; /* r1p3 */ cpu->midr = 0x411fc153; /* r1p3 */
cpu->isar.id_pfr0 = 0x0131; SET_IDREG(isar, ID_PFR0, 0x0131);
cpu->isar.id_pfr1 = 0x001; SET_IDREG(isar, ID_PFR1, 0x001);
cpu->isar.id_dfr0 = 0x010400; cpu->isar.id_dfr0 = 0x010400;
cpu->id_afr0 = 0x0; cpu->id_afr0 = 0x0;
cpu->isar.id_mmfr0 = 0x0210030; cpu->isar.id_mmfr0 = 0x0210030;
@ -748,8 +748,8 @@ static void cortex_r52_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8144c004; cpu->ctr = 0x8144c004;
cpu->reset_sctlr = 0x30c50838; cpu->reset_sctlr = 0x30c50838;
cpu->isar.id_pfr0 = 0x00000131; SET_IDREG(isar, ID_PFR0, 0x00000131);
cpu->isar.id_pfr1 = 0x10111001; SET_IDREG(isar, ID_PFR1, 0x10111001);
cpu->isar.id_dfr0 = 0x03010006; cpu->isar.id_dfr0 = 0x03010006;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00211040; cpu->isar.id_mmfr0 = 0x00211040;
@ -980,8 +980,8 @@ static void arm_max_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004; cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838; cpu->reset_sctlr = 0x00c50838;
cpu->isar.id_pfr0 = 0x00000131; SET_IDREG(isar, ID_PFR0, 0x00000131);
cpu->isar.id_pfr1 = 0x00011011; SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;

44
target/arm/tcg/cpu64.c
View file

@ -49,8 +49,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->midr = 0x411fd040; cpu->midr = 0x411fd040;
cpu->revidr = 0; cpu->revidr = 0;
cpu->ctr = 0x84448004; cpu->ctr = 0x84448004;
cpu->isar.id_pfr0 = 0x00000131; SET_IDREG(isar, ID_PFR0, 0x00000131);
cpu->isar.id_pfr1 = 0x00011011; SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;
@ -241,9 +241,9 @@ static void aarch64_a55_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000; cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211; cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110; cpu->isar.id_mmfr4 = 0x00021110;
cpu->isar.id_pfr0 = 0x10010131; SET_IDREG(isar, ID_PFR0, 0x10010131);
cpu->isar.id_pfr1 = 0x00011011; SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_pfr2 = 0x00000011; SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x412FD050; /* r2p0 */ cpu->midr = 0x412FD050; /* r2p0 */
cpu->revidr = 0; cpu->revidr = 0;
@ -295,8 +295,8 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004; cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838; cpu->reset_sctlr = 0x00c50838;
cpu->isar.id_pfr0 = 0x00000131; SET_IDREG(isar, ID_PFR0, 0x00000131);
cpu->isar.id_pfr1 = 0x00011011; SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;
@ -374,9 +374,9 @@ static void aarch64_a76_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000; cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211; cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110; cpu->isar.id_mmfr4 = 0x00021110;
cpu->isar.id_pfr0 = 0x10010131; SET_IDREG(isar, ID_PFR0, 0x10010131);
cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_pfr2 = 0x00000011; SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x414fd0b1; /* r4p1 */ cpu->midr = 0x414fd0b1; /* r4p1 */
cpu->revidr = 0; cpu->revidr = 0;
@ -622,9 +622,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000; cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211; cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110; cpu->isar.id_mmfr4 = 0x00021110;
cpu->isar.id_pfr0 = 0x10010131; SET_IDREG(isar, ID_PFR0, 0x10010131);
cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_pfr2 = 0x00000011; SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x414fd0c1; /* r4p1 */ cpu->midr = 0x414fd0c1; /* r4p1 */
cpu->revidr = 0; cpu->revidr = 0;
@ -701,9 +701,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000; cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211; cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x01021110; cpu->isar.id_mmfr4 = 0x01021110;
cpu->isar.id_pfr0 = 0x21110131; SET_IDREG(isar, ID_PFR0, 0x21110131);
cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_pfr2 = 0x00000011; SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x411FD402; /* r1p2 */ cpu->midr = 0x411FD402; /* r1p2 */
cpu->revidr = 0; cpu->revidr = 0;
@ -902,8 +902,8 @@ static void aarch64_a710_initfn(Object *obj)
/* Ordered by Section B.4: AArch64 registers */ /* Ordered by Section B.4: AArch64 registers */
cpu->midr = 0x412FD471; /* r2p1 */ cpu->midr = 0x412FD471; /* r2p1 */
cpu->revidr = 0; cpu->revidr = 0;
cpu->isar.id_pfr0 = 0x21110131; SET_IDREG(isar, ID_PFR0, 0x21110131);
cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_dfr0 = 0x16011099; cpu->isar.id_dfr0 = 0x16011099;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;
@ -921,7 +921,7 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110222; cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111; cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->isar.id_pfr2 = 0x00000011; SET_IDREG(isar, ID_PFR2, 0x00000011);
SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */ SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
@ -1004,8 +1004,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
/* Ordered by Section B.5: AArch64 ID registers */ /* Ordered by Section B.5: AArch64 ID registers */
cpu->midr = 0x410FD493; /* r0p3 */ cpu->midr = 0x410FD493; /* r0p3 */
cpu->revidr = 0; cpu->revidr = 0;
cpu->isar.id_pfr0 = 0x21110131; SET_IDREG(isar, ID_PFR0, 0x21110131);
cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_dfr0 = 0x16011099; cpu->isar.id_dfr0 = 0x16011099;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;
@ -1023,7 +1023,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110222; cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111; cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->isar.id_pfr2 = 0x00000011; SET_IDREG(isar, ID_PFR2, 0x00000011);
SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */ SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */