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target/nios2: Split mmu_write

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Create three separate functions for the three separate registers.
Avoid extra dispatch through op_helper.c.
Dispatch to the correct function in translation.
Clean up the ifdefs in wrctl.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-02-26 01:27:32 -10:00
parent 0b6e8f5b23
commit 304c05df7c
4 changed files with 104 additions and 111 deletions
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4
target/nios2/helper.h
View file

@ -21,6 +21,8 @@
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_3(mmu_write, void, env, i32, i32)
DEF_HELPER_2(mmu_write_tlbacc, void, env, i32)
DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32)
DEF_HELPER_2(mmu_write_pteaddr, void, env, i32)
DEF_HELPER_1(check_interrupts, void, env)
#endif

22
target/nios2/mmu.c
View file

@ -23,6 +23,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "mmu.h"
#include "exec/helper-proto.h"
#include "trace/trace-target_nios2.h"
@ -80,13 +81,11 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
}
}
void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
{
CPUState *cs = env_cpu(env);
Nios2CPU *cpu = env_archcpu(env);
switch (rn) {
case CR_TLBACC:
trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT,
(v & CR_TLBACC_C) ? 'C' : '.',
(v & CR_TLBACC_R) ? 'R' : '.',
@ -126,9 +125,12 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
/* Writes to TLBACC don't change the read-back value */
env->mmu.tlbacc_wr = v;
break;
}
void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
{
Nios2CPU *cpu = env_archcpu(env);
case CR_TLBMISC:
trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
(v & CR_TLBMISC_RD) ? 'R' : '.',
(v & CR_TLBMISC_WR) ? 'W' : '.',
@ -165,9 +167,10 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
}
env->mmu.tlbmisc_wr = v;
break;
}
case CR_PTEADDR:
void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v)
{
trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT,
(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT);
@ -175,11 +178,6 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
(env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK);
env->mmu.pteaddr_wr = v;
break;
default:
break;
}
}
void mmu_init(CPUNios2State *env)

5
target/nios2/op_helper.c
View file

@ -26,11 +26,6 @@
#include "qemu/main-loop.h"
#if !defined(CONFIG_USER_ONLY)
void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
{
mmu_write(env, rn, v);
}
static void nios2_check_interrupts(CPUNios2State *env)
{
if (env->irq_pending &&

26
target/nios2/translate.c
View file

@ -461,30 +461,28 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
/* ctlN <- rA */
static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
gen_check_supervisor(dc);
#ifndef CONFIG_USER_ONLY
R_TYPE(instr, code);
TCGv v = load_gpr(dc, instr.a);
switch (instr.imm5 + CR_BASE) {
case CR_PTEADDR:
case CR_TLBACC:
case CR_TLBMISC:
{
#if !defined(CONFIG_USER_ONLY)
TCGv_i32 tmp = tcg_const_i32(instr.imm5 + CR_BASE);
gen_helper_mmu_write(cpu_env, tmp, load_gpr(dc, instr.a));
tcg_temp_free_i32(tmp);
#endif
gen_helper_mmu_write_pteaddr(cpu_env, v);
break;
case CR_TLBACC:
gen_helper_mmu_write_tlbacc(cpu_env, v);
break;
case CR_TLBMISC:
gen_helper_mmu_write_tlbmisc(cpu_env, v);
break;
}
default:
tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], load_gpr(dc, instr.a));
tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
break;
}
/* If interrupts were enabled using WRCTL, trigger them. */
#if !defined(CONFIG_USER_ONLY)
if ((instr.imm5 + CR_BASE) == CR_STATUS) {
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();