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target/nios2: Split mmu_write

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Create three separate functions for the three separate registers.
Avoid extra dispatch through op_helper.c.
Dispatch to the correct function in translation.
Clean up the ifdefs in wrctl.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-02-26 01:27:32 -10:00
parent 0b6e8f5b23
commit 304c05df7c
4 changed files with 104 additions and 111 deletions
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26
target/nios2/translate.c
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@ -461,30 +461,28 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
/* ctlN <- rA */
static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
gen_check_supervisor(dc);
#ifndef CONFIG_USER_ONLY
R_TYPE(instr, code);
TCGv v = load_gpr(dc, instr.a);
switch (instr.imm5 + CR_BASE) {
case CR_PTEADDR:
case CR_TLBACC:
case CR_TLBMISC:
{
#if !defined(CONFIG_USER_ONLY)
TCGv_i32 tmp = tcg_const_i32(instr.imm5 + CR_BASE);
gen_helper_mmu_write(cpu_env, tmp, load_gpr(dc, instr.a));
tcg_temp_free_i32(tmp);
#endif
gen_helper_mmu_write_pteaddr(cpu_env, v);
break;
case CR_TLBACC:
gen_helper_mmu_write_tlbacc(cpu_env, v);
break;
case CR_TLBMISC:
gen_helper_mmu_write_tlbmisc(cpu_env, v);
break;
}
default:
tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], load_gpr(dc, instr.a));
tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
break;
}
/* If interrupts were enabled using WRCTL, trigger them. */
#if !defined(CONFIG_USER_ONLY)
if ((instr.imm5 + CR_BASE) == CR_STATUS) {
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();