motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-02 23:33:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target-openrisc: Move cpu_gdb_{read,write}_register()

Browse source 
Reviewed-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-07-07 12:40:38 +02:00
parent 814ac26c2d
commit 30028739eb
2 changed files with 78 additions and 56 deletions
Download patch file Download diff file Expand all files Collapse all files

57
gdbstub.c
View file

@ -554,63 +554,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined(TARGET_OPENRISC)
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->gpr[n]);
} else {
switch (n) {
case 32: /* PPC */
GET_REG32(env->ppc);
#include "target-openrisc/gdbstub.c"
case 33: /* NPC */
GET_REG32(env->npc);
case 34: /* SR */
GET_REG32(env->sr);
default:
break;
}
}
return 0;
}
static int cpu_gdb_write_register(CPUOpenRISCState *env,
uint8_t *mem_buf, int n)
{
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
return 0;
}
tmp = ldl_p(mem_buf);
if (n < 32) {
env->gpr[n] = tmp;
} else {
switch (n) {
case 32: /* PPC */
env->ppc = tmp;
break;
case 33: /* NPC */
env->npc = tmp;
break;
case 34: /* SR */
env->sr = tmp;
break;
default:
break;
}
}
return 4;
}
#elif defined (TARGET_SH4)
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */