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tcg/tci: Remove TCG_CONST
Restrict all operands to registers. All constants will be forced into registers by the middle-end. Removing the difference in how immediate integers were encoded will allow more code to be shared between 32-bit and 64-bit operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
552672bae6
commit
2f74f45e32
4 changed files with 89 additions and 194 deletions
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@ -10,16 +10,12 @@
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I2(r, r)
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C_O0_I2(r, ri)
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C_O0_I3(r, r, r)
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C_O0_I4(r, r, ri, ri)
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C_O0_I4(r, r, r, r)
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C_O1_I1(r, r)
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C_O1_I2(r, 0, r)
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C_O1_I2(r, ri, ri)
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C_O1_I2(r, r, r)
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C_O1_I2(r, r, ri)
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C_O1_I4(r, r, r, ri, ri)
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C_O1_I4(r, r, r, r, r)
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C_O2_I1(r, r, r)
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C_O2_I2(r, r, r, r)
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C_O2_I4(r, r, r, r, r, r)
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@ -92,8 +92,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_rem_i64:
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case INDEX_op_remu_i32:
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case INDEX_op_remu_i64:
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return C_O1_I2(r, r, r);
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case INDEX_op_add_i32:
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case INDEX_op_add_i64:
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case INDEX_op_sub_i32:
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@ -126,8 +124,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_rotl_i64:
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case INDEX_op_rotr_i32:
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case INDEX_op_rotr_i64:
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/* TODO: Does R, RI, RI result in faster code than R, R, RI? */
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return C_O1_I2(r, ri, ri);
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case INDEX_op_setcond_i32:
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case INDEX_op_setcond_i64:
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return C_O1_I2(r, r, r);
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i64:
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@ -135,11 +134,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_brcond_i32:
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case INDEX_op_brcond_i64:
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return C_O0_I2(r, ri);
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case INDEX_op_setcond_i32:
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case INDEX_op_setcond_i64:
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return C_O1_I2(r, r, ri);
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return C_O0_I2(r, r);
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#if TCG_TARGET_REG_BITS == 32
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/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
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@ -147,11 +142,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_sub2_i32:
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return C_O2_I4(r, r, r, r, r, r);
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case INDEX_op_brcond2_i32:
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return C_O0_I4(r, r, ri, ri);
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return C_O0_I4(r, r, r, r);
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case INDEX_op_mulu2_i32:
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return C_O2_I2(r, r, r, r);
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case INDEX_op_setcond2_i32:
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return C_O1_I4(r, r, r, ri, ri);
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return C_O1_I4(r, r, r, r, r);
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#endif
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case INDEX_op_qemu_ld_i32:
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@ -294,44 +289,6 @@ static void tcg_out_r(TCGContext *s, TCGArg t0)
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tcg_out8(s, t0);
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}
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/* Write register or constant (native size). */
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static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
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{
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if (const_arg) {
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tcg_debug_assert(const_arg == 1);
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tcg_out8(s, TCG_CONST);
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tcg_out_i(s, arg);
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} else {
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tcg_out_r(s, arg);
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}
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}
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/* Write register or constant (32 bit). */
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static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
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{
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if (const_arg) {
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tcg_debug_assert(const_arg == 1);
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tcg_out8(s, TCG_CONST);
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tcg_out32(s, arg);
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} else {
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tcg_out_r(s, arg);
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}
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}
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#if TCG_TARGET_REG_BITS == 64
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/* Write register or constant (64 bit). */
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static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
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{
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if (const_arg) {
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tcg_debug_assert(const_arg == 1);
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tcg_out8(s, TCG_CONST);
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tcg_out64(s, arg);
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} else {
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tcg_out_r(s, arg);
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}
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}
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#endif
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/* Write label. */
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static void tci_out_label(TCGContext *s, TCGLabel *label)
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{
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@ -419,7 +376,7 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
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{
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uint8_t *old_code_ptr = s->code_ptr;
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tcg_out_op_t(s, INDEX_op_call);
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tcg_out_ri(s, 1, (uintptr_t)arg);
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tcg_out_i(s, (uintptr_t)arg);
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old_code_ptr[1] = s->code_ptr - old_code_ptr;
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}
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@ -453,7 +410,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_setcond_i32:
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tcg_out_r(s, args[0]);
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tcg_out_r(s, args[1]);
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tcg_out_ri32(s, const_args[2], args[2]);
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tcg_out_r(s, args[2]);
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tcg_out8(s, args[3]); /* condition */
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break;
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#if TCG_TARGET_REG_BITS == 32
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@ -462,15 +419,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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tcg_out_r(s, args[0]);
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tcg_out_r(s, args[1]);
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tcg_out_r(s, args[2]);
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tcg_out_ri32(s, const_args[3], args[3]);
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tcg_out_ri32(s, const_args[4], args[4]);
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tcg_out_r(s, args[3]);
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tcg_out_r(s, args[4]);
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tcg_out8(s, args[5]); /* condition */
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break;
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#elif TCG_TARGET_REG_BITS == 64
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case INDEX_op_setcond_i64:
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tcg_out_r(s, args[0]);
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tcg_out_r(s, args[1]);
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tcg_out_ri64(s, const_args[2], args[2]);
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tcg_out_r(s, args[2]);
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tcg_out8(s, args[3]); /* condition */
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break;
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#endif
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@ -516,8 +473,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
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case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
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tcg_out_r(s, args[0]);
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tcg_out_ri32(s, const_args[1], args[1]);
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tcg_out_ri32(s, const_args[2], args[2]);
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tcg_out_r(s, args[1]);
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tcg_out_r(s, args[2]);
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break;
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case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
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tcg_out_r(s, args[0]);
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@ -551,8 +508,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
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case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
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tcg_out_r(s, args[0]);
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tcg_out_ri64(s, const_args[1], args[1]);
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tcg_out_ri64(s, const_args[2], args[2]);
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tcg_out_r(s, args[1]);
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tcg_out_r(s, args[2]);
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break;
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case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
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tcg_out_r(s, args[0]);
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@ -565,7 +522,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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break;
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case INDEX_op_brcond_i64:
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tcg_out_r(s, args[0]);
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tcg_out_ri64(s, const_args[1], args[1]);
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tcg_out_r(s, args[1]);
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tcg_out8(s, args[2]); /* condition */
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tci_out_label(s, arg_label(args[3]));
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break;
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@ -599,8 +556,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
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case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
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tcg_out_r(s, args[0]);
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tcg_out_ri32(s, const_args[1], args[1]);
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tcg_out_ri32(s, const_args[2], args[2]);
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tcg_out_r(s, args[1]);
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tcg_out_r(s, args[2]);
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break;
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_add2_i32:
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@ -615,8 +572,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_brcond2_i32:
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tcg_out_r(s, args[0]);
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tcg_out_r(s, args[1]);
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tcg_out_ri32(s, const_args[2], args[2]);
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tcg_out_ri32(s, const_args[3], args[3]);
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tcg_out_r(s, args[2]);
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tcg_out_r(s, args[3]);
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tcg_out8(s, args[4]); /* condition */
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tci_out_label(s, arg_label(args[5]));
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break;
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@ -629,7 +586,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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#endif
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case INDEX_op_brcond_i32:
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tcg_out_r(s, args[0]);
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tcg_out_ri32(s, const_args[1], args[1]);
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tcg_out_r(s, args[1]);
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tcg_out8(s, args[2]); /* condition */
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tci_out_label(s, arg_label(args[3]));
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break;
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@ -157,9 +157,6 @@ typedef enum {
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TCG_AREG0 = TCG_REG_R14,
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TCG_REG_CALL_STACK = TCG_REG_R15,
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/* Special value UINT8_MAX is used by TCI to encode constant values. */
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TCG_CONST = UINT8_MAX
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} TCGReg;
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/* Used for function call generation. */
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