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target/sparc: Move FPACK16, FPACKFIX to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-11 21:36:35 -07:00
parent e2fa6bd1ad
commit 2f72264169
2 changed files with 42 additions and 15 deletions
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2
target/sparc/insns.decode
View file

@ -344,6 +344,8 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5
FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r
FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r
FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r
FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_r2
FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_r2
PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r
FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r

55
target/sparc/translate.c
View file

@ -756,6 +756,24 @@ static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_shli_tl(dst, dst, 2); tcg_gen_shli_tl(dst, dst, 2);
} }
static void gen_op_fpack16(TCGv_i32 dst, TCGv_i64 src)
{
#ifdef TARGET_SPARC64
gen_helper_fpack16(dst, cpu_gsr, src);
#else
g_assert_not_reached();
#endif
}
static void gen_op_fpackfix(TCGv_i32 dst, TCGv_i64 src)
{
#ifdef TARGET_SPARC64
gen_helper_fpackfix(dst, cpu_gsr, src);
#else
g_assert_not_reached();
#endif
}
static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2)
{ {
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
@ -4589,6 +4607,26 @@ TRANS(FABSs, ALL, do_ff, a, gen_op_fabss)
TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32)
TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32)
static bool do_fd(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_i32, TCGv_i64))
{
TCGv_i32 dst;
TCGv_i64 src;
if (gen_trap_ifnofpu(dc)) {
return true;
}
dst = gen_dest_fpr_F(dc);
src = gen_load_fpr_D(dc, a->rs);
func(dst, src);
gen_store_fpr_F(dc, a->rd, dst);
return advance_pc(dc);
}
TRANS(FPACK16, VIS1, do_fd, a, gen_op_fpack16)
TRANS(FPACKFIX, VIS1, do_fd, a, gen_op_fpackfix)
static bool do_env_ff(DisasContext *dc, arg_r_r *a, static bool do_env_ff(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) void (*func)(TCGv_i32, TCGv_env, TCGv_i32))
{ {
@ -5265,10 +5303,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
} else if (xop == 0x36) { } else if (xop == 0x36) {
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
/* VIS */ /* VIS */
TCGv_i64 cpu_src1_64, cpu_dst_64; TCGv_i64 cpu_dst_64;
TCGv_i32 cpu_dst_32; TCGv_i32 cpu_dst_32;
int opf = GET_FIELD_SP(insn, 5, 13); int opf = GET_FIELD_SP(insn, 5, 13);
int rs2 = GET_FIELD(insn, 27, 31);
int rd = GET_FIELD(insn, 2, 6); int rd = GET_FIELD(insn, 2, 6);
if (gen_trap_ifnofpu(dc)) { if (gen_trap_ifnofpu(dc)) {
@ -5351,21 +5388,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x02a: /* VIS I fcmpeq16 */ case 0x02a: /* VIS I fcmpeq16 */
case 0x02c: /* VIS I fcmpgt32 */ case 0x02c: /* VIS I fcmpgt32 */
case 0x02e: /* VIS I fcmpeq32 */ case 0x02e: /* VIS I fcmpeq32 */
g_assert_not_reached(); /* in decodetree */
case 0x03b: /* VIS I fpack16 */ case 0x03b: /* VIS I fpack16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_32 = gen_dest_fpr_F(dc);
gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x03d: /* VIS I fpackfix */ case 0x03d: /* VIS I fpackfix */
CHECK_FPU_FEATURE(dc, VIS1); g_assert_not_reached(); /* in decodetree */
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_32 = gen_dest_fpr_F(dc);
gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x060: /* VIS I fzero */ case 0x060: /* VIS I fzero */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
cpu_dst_64 = gen_dest_fpr_D(dc, rd); cpu_dst_64 = gen_dest_fpr_D(dc, rd);