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hw/arm/aspeed: Extract code common to all boards to a common file
aspeed_soc.c contains definitions specific to the AST2400 and AST2500 SoCs, but also some definitions for other AST SoCs: move them to a common file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Philippe Mathieu-Daudé
Cédric Le Goater
parent
cbe27c3ec3
commit
2f4ec77679
3 changed files with 115 additions and 96 deletions
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@ -585,99 +585,3 @@ static void aspeed_soc_register_types(void)
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};
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};
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type_init(aspeed_soc_register_types);
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type_init(aspeed_soc_register_types);
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qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
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{
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return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
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}
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bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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SerialMM *smm;
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for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
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smm = &s->uart[i];
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/* Chardev property is set by the machine. */
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qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
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qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
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qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
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qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
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if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
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return false;
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}
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sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
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aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
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}
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return true;
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}
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void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i = dev - ASPEED_DEV_UART1;
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g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
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qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
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}
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/*
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* SDMC should be realized first to get correct RAM size and max size
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* values
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*/
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bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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ram_addr_t ram_size, max_ram_size;
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ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
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&error_abort);
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max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
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&error_abort);
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memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
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max_ram_size);
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memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
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/*
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* Add a memory region beyond the RAM region to let firmwares scan
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* the address space with load/store and guess how much RAM the
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* SoC has.
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*/
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if (ram_size < max_ram_size) {
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DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
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qdev_prop_set_string(dev, "name", "ram-empty");
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qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
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if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
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return false;
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}
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memory_region_add_subregion_overlap(&s->dram_container, ram_size,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
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}
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memory_region_add_subregion(s->memory,
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sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
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return true;
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}
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void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
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{
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memory_region_add_subregion(s->memory, addr,
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sysbus_mmio_get_region(dev, n));
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}
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void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
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const char *name, hwaddr addr, uint64_t size)
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{
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qdev_prop_set_string(DEVICE(dev), "name", name);
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qdev_prop_set_uint64(DEVICE(dev), "size", size);
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sysbus_realize(dev, &error_abort);
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memory_region_add_subregion_overlap(s->memory, addr,
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sysbus_mmio_get_region(dev, 0), -1000);
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}
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114
hw/arm/aspeed_soc_common.c
Normal file
114
hw/arm/aspeed_soc_common.c
Normal file
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@ -0,0 +1,114 @@
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/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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* Jeremy Kerr <jk@ozlabs.org>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/char/serial.h"
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qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
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{
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return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
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}
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bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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SerialMM *smm;
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for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
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smm = &s->uart[i];
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/* Chardev property is set by the machine. */
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qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
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qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
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qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
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qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
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if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
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return false;
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}
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sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
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aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
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}
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return true;
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}
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void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i = dev - ASPEED_DEV_UART1;
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g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
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qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
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}
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/*
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* SDMC should be realized first to get correct RAM size and max size
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* values
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*/
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bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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ram_addr_t ram_size, max_ram_size;
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ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
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&error_abort);
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max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
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&error_abort);
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memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
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max_ram_size);
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memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
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/*
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* Add a memory region beyond the RAM region to let firmwares scan
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* the address space with load/store and guess how much RAM the
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* SoC has.
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*/
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if (ram_size < max_ram_size) {
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DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
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qdev_prop_set_string(dev, "name", "ram-empty");
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qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
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if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
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return false;
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}
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memory_region_add_subregion_overlap(&s->dram_container, ram_size,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
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}
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memory_region_add_subregion(s->memory,
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sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
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return true;
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}
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void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
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{
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memory_region_add_subregion(s->memory, addr,
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sysbus_mmio_get_region(dev, n));
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}
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void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
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const char *name, hwaddr addr, uint64_t size)
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{
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qdev_prop_set_string(DEVICE(dev), "name", name);
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qdev_prop_set_uint64(DEVICE(dev), "size", size);
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sysbus_realize(dev, &error_abort);
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memory_region_add_subregion_overlap(s->memory, addr,
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sysbus_mmio_get_region(dev, 0), -1000);
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}
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@ -50,6 +50,7 @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
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arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
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arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
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'aspeed_soc.c',
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'aspeed_soc.c',
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'aspeed.c',
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'aspeed.c',
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'aspeed_soc_common.c',
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'aspeed_ast2600.c',
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'aspeed_ast2600.c',
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'aspeed_ast10x0.c',
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'aspeed_ast10x0.c',
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'aspeed_eeprom.c',
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'aspeed_eeprom.c',
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