target-alpha: Inline call_pal

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2014-09-16 12:35:59 -07:00
parent 591243846f
commit 2f458b7c31
3 changed files with 24 additions and 18 deletions

View file

@ -92,7 +92,6 @@ DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64)
#if !defined (CONFIG_USER_ONLY)
DEF_HELPER_2(hw_ret, void, env, i64)
DEF_HELPER_3(call_pal, void, env, i64, i64)
DEF_HELPER_2(ldl_phys, i64, env, i64)
DEF_HELPER_2(ldq_phys, i64, env, i64)

View file

@ -48,14 +48,6 @@ void helper_hw_ret(CPUAlphaState *env, uint64_t a)
env->pal_mode = a & 1;
}
void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs)
{
int pal_mode = env->pal_mode;
env->exc_addr = pc | pal_mode;
env->pc = env->palbr + entry_ofs;
env->pal_mode = 1;
}
void helper_tbia(CPUAlphaState *env)
{
tlb_flush(CPU(alpha_env_get_cpu(env)), 1);

View file

@ -42,6 +42,9 @@ typedef struct DisasContext DisasContext;
struct DisasContext {
struct TranslationBlock *tb;
uint64_t pc;
#ifndef CONFIG_USER_ONLY
uint64_t palbr;
#endif
int mem_idx;
/* Current rounding mode for this TB. */
@ -1206,28 +1209,39 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
return gen_excp(ctx, EXCP_CALL_PAL, palcode);
#else
{
TCGv pc = tcg_const_i64(ctx->pc);
TCGv entry = tcg_const_i64(palcode & 0x80
TCGv tmp = tcg_temp_new();
uint64_t exc_addr = ctx->pc;
uint64_t entry = ctx->palbr;
if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
exc_addr |= 1;
} else {
tcg_gen_movi_i64(tmp, 1);
tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode));
}
tcg_gen_movi_i64(tmp, exc_addr);
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
tcg_temp_free(tmp);
entry += (palcode & 0x80
? 0x2000 + (palcode - 0x80) * 64
: 0x1000 + palcode * 64);
gen_helper_call_pal(cpu_env, pc, entry);
tcg_temp_free(entry);
tcg_temp_free(pc);
/* Since the destination is running in PALmode, we don't really
need the page permissions check. We'll see the existence of
the page when we create the TB, and we'll flush all TBs if
we change the PAL base register. */
if (!ctx->singlestep_enabled && !(ctx->tb->cflags & CF_LAST_IO)) {
tcg_gen_goto_tb(0);
tcg_gen_movi_i64(cpu_pc, entry);
tcg_gen_exit_tb((uintptr_t)ctx->tb);
return EXIT_GOTO_TB;
}
} else {
tcg_gen_movi_i64(cpu_pc, entry);
return EXIT_PC_UPDATED;
}
}
#endif
}
@ -2861,6 +2875,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
#ifdef CONFIG_USER_ONLY
ctx.ir = cpu_std_ir;
#else
ctx.palbr = env->palbr;
ctx.ir = (tb->flags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir);
#endif