motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-11 03:24:58 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/mips: Style improvements in cp0_timer.c

Browse source 
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1566216496-17375-7-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-19 14:07:45 +02:00
parent 50d69ee0d8
commit 2f0d019672
1 changed files with 23 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

30
target/mips/cp0_timer.c
View file

@ -43,8 +43,10 @@ uint32_t cpu_mips_get_random (CPUMIPSState *env)
/* Don't return same value twice, so get another value */
do {
/* Use a simple algorithm of Linear Congruential Generator
* from ISO/IEC 9899 standard. */
/*
* Use a simple algorithm of Linear Congruential Generator
* from ISO/IEC 9899 standard.
*/
seed = 1103515245 * seed + 12345;
idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
} while (idx == prev_idx);
@ -99,9 +101,9 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
* So env->timer may be NULL, which is also the case with KVM enabled so
* treat timer as disabled in that case.
*/
if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer)
if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) {
env->CP0_Count = count;
else {
} else {
/* Store new count register */
env->CP0_Count = count -
(uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
@ -113,10 +115,12 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
{
env->CP0_Compare = value;
if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
cpu_mips_timer_update(env);
if (env->insn_flags & ISA_MIPS32R2)
}
if (env->insn_flags & ISA_MIPS32R2) {
env->CP0_Cause &= ~(1 << CP0Ca_TI);
}
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
@ -137,16 +141,16 @@ static void mips_timer_cb (void *opaque)
CPUMIPSState *env;
env = opaque;
#if 0
qemu_log("%s\n", __func__);
#endif
if (env->CP0_Cause & (1 << CP0Ca_DC))
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return;
}
/* ??? This callback should occur when the counter is exactly equal to
the comparator value. Offset the count by one to avoid immediately
retriggering the callback before any virtual time has passed. */
/*
* ??? This callback should occur when the counter is exactly equal to
* the comparator value. Offset the count by one to avoid immediately
* retriggering the callback before any virtual time has passed.
*/
env->CP0_Count++;
cpu_mips_timer_expire(env);
env->CP0_Count--;