mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 00:33:55 -06:00
Stand-alone SCI/SCIF emulation code, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3270 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
cd1a3f6840
commit
2f062c7227
6 changed files with 325 additions and 585 deletions
345
hw/sh7750.c
345
hw/sh7750.c
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@ -27,13 +27,6 @@
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#include "sh7750_regs.h"
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#include "sh7750_regnames.h"
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typedef struct {
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uint8_t data[16];
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uint8_t length; /* Number of characters in the FIFO */
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uint8_t write_idx; /* Index of first character to write */
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uint8_t read_idx; /* Index of first character to read */
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} fifo;
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#define NB_DEVICES 4
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typedef struct SH7750State {
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@ -43,27 +36,6 @@ typedef struct SH7750State {
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uint32_t periph_freq;
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/* SDRAM controller */
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uint16_t rfcr;
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/* First serial port */
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CharDriverState *serial1;
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uint8_t scscr1;
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uint8_t scsmr1;
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uint8_t scbrr1;
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uint8_t scssr1;
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uint8_t scssr1_read;
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uint8_t sctsr1;
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uint8_t sctsr1_loaded;
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uint8_t sctdr1;
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uint8_t scrdr1;
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/* Second serial port */
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CharDriverState *serial2;
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uint16_t sclsr2;
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uint16_t scscr2;
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uint16_t scfcr2;
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uint16_t scfsr2;
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uint16_t scsmr2;
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uint8_t scbrr2;
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fifo serial2_receive_fifo;
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fifo serial2_transmit_fifo;
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/* IO ports */
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uint16_t gpioic;
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uint32_t pctra;
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@ -84,263 +56,6 @@ typedef struct SH7750State {
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} SH7750State;
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/**********************************************************************
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First serial port
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**********************************************************************/
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static int serial1_can_receive(void *opaque)
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{
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SH7750State *s = opaque;
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return s->scscr1 & SH7750_SCSCR_RE;
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}
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static void serial1_receive_char(SH7750State * s, uint8_t c)
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{
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if (s->scssr1 & SH7750_SCSSR1_RDRF) {
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s->scssr1 |= SH7750_SCSSR1_ORER;
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return;
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}
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s->scrdr1 = c;
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s->scssr1 |= SH7750_SCSSR1_RDRF;
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}
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static void serial1_receive(void *opaque, const uint8_t * buf, int size)
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{
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SH7750State *s = opaque;
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int i;
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for (i = 0; i < size; i++) {
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serial1_receive_char(s, buf[i]);
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}
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}
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static void serial1_event(void *opaque, int event)
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{
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assert(0);
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}
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static void serial1_maybe_send(SH7750State * s)
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{
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uint8_t c;
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if (s->scssr1 & SH7750_SCSSR1_TDRE)
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return;
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c = s->sctdr1;
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s->scssr1 |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
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if (s->scscr1 & SH7750_SCSCR_TIE) {
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fprintf(stderr, "interrupts for serial port 1 not implemented\n");
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assert(0);
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}
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/* XXXXX Check for errors in write */
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qemu_chr_write(s->serial1, &c, 1);
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}
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static void serial1_change_scssr1(SH7750State * s, uint8_t mem_value)
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{
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uint8_t new_flags;
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/* If transmit disable, TDRE and TEND stays up */
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if ((s->scscr1 & SH7750_SCSCR_TE) == 0) {
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mem_value |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
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}
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/* Only clear bits which have been read before and do not set any bit
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in the flags */
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new_flags = s->scssr1 & ~s->scssr1_read; /* Preserve unread flags */
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new_flags &= mem_value | ~s->scssr1_read; /* Clear read flags */
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s->scssr1 = (new_flags & 0xf8) | (mem_value & 1);
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s->scssr1_read &= mem_value;
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/* If TDRE has been cleared, TEND will also be cleared */
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if ((s->scssr1 & SH7750_SCSSR1_TDRE) == 0) {
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s->scssr1 &= ~SH7750_SCSSR1_TEND;
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}
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/* Check for transmission to start */
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serial1_maybe_send(s);
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}
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static void serial1_update_parameters(SH7750State * s)
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{
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QEMUSerialSetParams ssp;
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if (s->scsmr1 & SH7750_SCSMR_CHR_7)
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ssp.data_bits = 7;
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else
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ssp.data_bits = 8;
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if (s->scsmr1 & SH7750_SCSMR_PE) {
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if (s->scsmr1 & SH7750_SCSMR_PM_ODD)
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ssp.parity = 'O';
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else
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ssp.parity = 'E';
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} else
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ssp.parity = 'N';
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if (s->scsmr1 & SH7750_SCSMR_STOP_2)
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ssp.stop_bits = 2;
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else
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ssp.stop_bits = 1;
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fprintf(stderr, "SCSMR1=%04x SCBRR1=%02x\n", s->scsmr1, s->scbrr1);
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ssp.speed = s->periph_freq /
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(32 * s->scbrr1 * (1 << (2 * (s->scsmr1 & 3)))) - 1;
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fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
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ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
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qemu_chr_ioctl(s->serial1, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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}
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static void scscr1_changed(SH7750State * s)
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{
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if (s->scscr1 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
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if (!s->serial1) {
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fprintf(stderr, "serial port 1 not bound to anything\n");
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assert(0);
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}
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serial1_update_parameters(s);
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}
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if ((s->scscr1 & SH7750_SCSCR_RE) == 0) {
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s->scssr1 |= SH7750_SCSSR1_TDRE;
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}
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}
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static void init_serial1(SH7750State * s, int serial_nb)
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{
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CharDriverState *chr;
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s->scssr1 = 0x84;
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chr = serial_hds[serial_nb];
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if (!chr) {
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fprintf(stderr,
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"no serial port associated to SH7750 first serial port\n");
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return;
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}
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s->serial1 = chr;
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qemu_chr_add_handlers(chr, serial1_can_receive,
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serial1_receive, serial1_event, s);
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}
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/**********************************************************************
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Second serial port
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**********************************************************************/
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static int serial2_can_receive(void *opaque)
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{
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SH7750State *s = opaque;
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static uint8_t max_fifo_size[] = { 15, 1, 4, 6, 8, 10, 12, 14 };
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return s->serial2_receive_fifo.length <
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max_fifo_size[(s->scfcr2 >> 9) & 7];
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}
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static void serial2_adjust_receive_flags(SH7750State * s)
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{
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static uint8_t max_fifo_size[] = { 1, 4, 8, 14 };
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/* XXXXX Add interrupt generation */
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if (s->serial2_receive_fifo.length >=
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max_fifo_size[(s->scfcr2 >> 7) & 3]) {
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s->scfsr2 |= SH7750_SCFSR2_RDF;
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s->scfsr2 &= ~SH7750_SCFSR2_DR;
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} else {
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s->scfsr2 &= ~SH7750_SCFSR2_RDF;
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if (s->serial2_receive_fifo.length > 0)
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s->scfsr2 |= SH7750_SCFSR2_DR;
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else
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s->scfsr2 &= ~SH7750_SCFSR2_DR;
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}
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}
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static void serial2_append_char(SH7750State * s, uint8_t c)
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{
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if (s->serial2_receive_fifo.length == 16) {
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/* Overflow */
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s->sclsr2 |= SH7750_SCLSR2_ORER;
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return;
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}
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s->serial2_receive_fifo.data[s->serial2_receive_fifo.write_idx++] = c;
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s->serial2_receive_fifo.length++;
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serial2_adjust_receive_flags(s);
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}
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static void serial2_receive(void *opaque, const uint8_t * buf, int size)
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{
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SH7750State *s = opaque;
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int i;
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for (i = 0; i < size; i++)
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serial2_append_char(s, buf[i]);
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}
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static void serial2_event(void *opaque, int event)
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{
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/* XXXXX */
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assert(0);
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}
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static void serial2_update_parameters(SH7750State * s)
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{
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QEMUSerialSetParams ssp;
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if (s->scsmr2 & SH7750_SCSMR_CHR_7)
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ssp.data_bits = 7;
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else
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ssp.data_bits = 8;
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if (s->scsmr2 & SH7750_SCSMR_PE) {
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if (s->scsmr2 & SH7750_SCSMR_PM_ODD)
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ssp.parity = 'O';
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else
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ssp.parity = 'E';
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} else
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ssp.parity = 'N';
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if (s->scsmr2 & SH7750_SCSMR_STOP_2)
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ssp.stop_bits = 2;
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else
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ssp.stop_bits = 1;
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fprintf(stderr, "SCSMR2=%04x SCBRR2=%02x\n", s->scsmr2, s->scbrr2);
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ssp.speed = s->periph_freq /
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(32 * s->scbrr2 * (1 << (2 * (s->scsmr2 & 3)))) - 1;
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fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
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ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
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qemu_chr_ioctl(s->serial2, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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}
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static void scscr2_changed(SH7750State * s)
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{
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if (s->scscr2 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
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if (!s->serial2) {
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fprintf(stderr, "serial port 2 not bound to anything\n");
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assert(0);
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}
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serial2_update_parameters(s);
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}
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}
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static void init_serial2(SH7750State * s, int serial_nb)
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{
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CharDriverState *chr;
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s->scfsr2 = 0x0060;
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chr = serial_hds[serial_nb];
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if (!chr) {
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fprintf(stderr,
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"no serial port associated to SH7750 second serial port\n");
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return;
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}
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s->serial2 = chr;
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qemu_chr_add_handlers(chr, serial2_can_receive,
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serial2_receive, serial1_event, s);
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}
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static void init_serial_ports(SH7750State * s)
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{
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init_serial1(s, 0);
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init_serial2(s, 1);
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}
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/**********************************************************************
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I/O ports
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@ -472,17 +187,7 @@ static void ignore_access(const char *kind, target_phys_addr_t addr)
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static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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SH7750State *s = opaque;
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uint8_t r;
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switch (addr) {
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case SH7750_SCSSR1_A7:
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r = s->scssr1;
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s->scssr1_read |= r;
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return s->scssr1;
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case SH7750_SCRDR1_A7:
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s->scssr1 &= ~SH7750_SCSSR1_RDRF;
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return s->scrdr1;
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default:
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error_access("byte read", addr);
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assert(0);
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@ -492,20 +197,12 @@ static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
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static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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SH7750State *s = opaque;
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uint16_t r;
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switch (addr) {
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case SH7750_RFCR_A7:
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fprintf(stderr,
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"Read access to refresh count register, incrementing\n");
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return s->rfcr++;
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case SH7750_SCLSR2_A7:
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/* Read and clear overflow bit */
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r = s->sclsr2;
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s->sclsr2 = 0;
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return r;
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case SH7750_SCSFR2_A7:
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return s->scfsr2;
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case SH7750_PDTRA_A7:
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return porta_lines(s);
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case SH7750_PDTRB_A7:
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@ -554,34 +251,12 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
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static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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{
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SH7750State *s = opaque;
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switch (addr) {
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/* PRECHARGE ? XXXXX */
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case SH7750_PRECHARGE0_A7:
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case SH7750_PRECHARGE1_A7:
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ignore_access("byte write", addr);
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return;
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case SH7750_SCBRR2_A7:
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s->scbrr2 = mem_value;
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return;
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case SH7750_SCSCR1_A7:
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s->scscr1 = mem_value;
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scscr1_changed(s);
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return;
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case SH7750_SCSMR1_A7:
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s->scsmr1 = mem_value;
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return;
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case SH7750_SCBRR1_A7:
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s->scbrr1 = mem_value;
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return;
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case SH7750_SCTDR1_A7:
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s->scssr1 &= ~SH7750_SCSSR1_TEND;
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s->sctdr1 = mem_value;
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return;
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case SH7750_SCSSR1_A7:
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serial1_change_scssr1(s, mem_value);
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return;
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default:
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error_access("byte write", addr);
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assert(0);
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@ -596,8 +271,6 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
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switch (addr) {
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/* SDRAM controller */
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case SH7750_SCBRR1_A7:
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case SH7750_SCBRR2_A7:
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case SH7750_BCR2_A7:
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case SH7750_BCR3_A7:
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case SH7750_RTCOR_A7:
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@ -620,19 +293,6 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
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fprintf(stderr, "Write access to refresh count register\n");
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s->rfcr = mem_value;
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return;
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case SH7750_SCLSR2_A7:
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s->sclsr2 = mem_value;
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return;
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case SH7750_SCSCR2_A7:
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s->scscr2 = mem_value;
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scscr2_changed(s);
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return;
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case SH7750_SCFCR2_A7:
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s->scfcr2 = mem_value;
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return;
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case SH7750_SCSMR2_A7:
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s->scsmr2 = mem_value;
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return;
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case SH7750_GPIOIC_A7:
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s->gpioic = mem_value;
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if (mem_value != 0) {
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@ -734,7 +394,10 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
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sh7750_mem_read,
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sh7750_mem_write, s);
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cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
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init_serial_ports(s);
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sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
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sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
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s->periph_freq, serial_hds[1]);
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tmu012_init(0x1fd80000,
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TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
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