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target/microblaze: Split out MSR from env->sregs

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Continue eliminating the sregs array in favor of individual members.
Does not correct the width of MSR, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-19 21:41:10 -07:00
parent 76e8187d00
commit 2e5282caa8
6 changed files with 51 additions and 49 deletions
Download patch file Download diff file Expand all files Collapse all files

49
target/microblaze/helper.c
View file

@ -117,7 +117,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
/* IMM flag cannot propagate across a branch and into the dslot. */
assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */
env->res_addr = RES_ADDR_NONE;
switch (cs->exception_index) {
case EXCP_HW_EXCP:
@ -136,11 +136,11 @@ void mb_cpu_do_interrupt(CPUState *cs)
}
/* Disable the MMU. */
t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->sregs[SR_MSR] |= t;
t = (env->msr & (MSR_VM | MSR_UM)) << 1;
env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->msr |= t;
/* Exception in progress. */
env->sregs[SR_MSR] |= MSR_EIP;
env->msr |= MSR_EIP;
qemu_log_mask(CPU_LOG_INT,
"hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
@ -179,11 +179,11 @@ void mb_cpu_do_interrupt(CPUState *cs)
}
/* Disable the MMU. */
t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->sregs[SR_MSR] |= t;
t = (env->msr & (MSR_VM | MSR_UM)) << 1;
env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->msr |= t;
/* Exception in progress. */
env->sregs[SR_MSR] |= MSR_EIP;
env->msr |= MSR_EIP;
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%" PRIx64 " ear=%" PRIx64 " "
@ -195,11 +195,11 @@ void mb_cpu_do_interrupt(CPUState *cs)
break;
case EXCP_IRQ:
assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
assert(env->sregs[SR_MSR] & MSR_IE);
assert(!(env->msr & (MSR_EIP | MSR_BIP)));
assert(env->msr & MSR_IE);
assert(!(env->iflags & D_FLAG));
t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
t = (env->msr & (MSR_VM | MSR_UM)) << 1;
#if 0
#include "disas/disas.h"
@ -216,7 +216,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log(
"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
env->pc, env->sregs[SR_MSR], t, env->iflags,
env->pc, env->msr, t, env->iflags,
sym);
log_cpu_state(cs, 0);
@ -226,11 +226,10 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "
"iflags=%x\n",
env->pc, env->sregs[SR_MSR], t, env->iflags);
env->pc, env->msr, t, env->iflags);
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
| MSR_UM | MSR_IE);
env->sregs[SR_MSR] |= t;
env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE);
env->msr |= t;
env->regs[14] = env->pc;
env->pc = cpu->cfg.base_vectors + 0x10;
@ -241,18 +240,18 @@ void mb_cpu_do_interrupt(CPUState *cs)
case EXCP_HW_BREAK:
assert(!(env->iflags & IMM_FLAG));
assert(!(env->iflags & D_FLAG));
t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
t = (env->msr & (MSR_VM | MSR_UM)) << 1;
qemu_log_mask(CPU_LOG_INT,
"break at pc=%" PRIx64 " msr=%" PRIx64 " %x "
"iflags=%x\n",
env->pc, env->sregs[SR_MSR], t, env->iflags);
env->pc, env->msr, t, env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->sregs[SR_MSR] |= t;
env->sregs[SR_MSR] |= MSR_BIP;
env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->msr |= t;
env->msr |= MSR_BIP;
if (cs->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->pc;
env->sregs[SR_MSR] |= MSR_BIP;
env->msr |= MSR_BIP;
env->pc = cpu->cfg.base_vectors + 0x18;
} else
env->pc = env->btarget;
@ -293,8 +292,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
CPUMBState *env = &cpu->env;
if ((interrupt_request & CPU_INTERRUPT_HARD)
&& (env->sregs[SR_MSR] & MSR_IE)
&& !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
&& (env->msr & MSR_IE)
&& !(env->msr & (MSR_EIP | MSR_BIP))
&& !(env->iflags & (D_FLAG | IMM_FLAG))) {
cs->exception_index = EXCP_IRQ;
mb_cpu_do_interrupt(cs);