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ppc patch queue 2018-05-04
Second patch of patches for qemu-2.13 (or whatever the version ends up being called). Highlights are: * Preliminary patches for POWER9 hash MMU support for powernv * A number of cleanups fo pseries startup and LPCR handling * Remove support for explicitly allocated RMAs (which require kernel support that's been gone for 3+ years) * Some mac_newworld cleanups * A few bugfixes -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAlrr6p8ACgkQbDjKyiDZ s5IxDQ/+NIZzD6xmMW0AtTes73Sn5uy3vB5utv/mgjbKuoovCE+FRtVXAPVlc41O q6Y8f0PWCfTbJb+G/XusSyQX9kc/anmmyQdrWuCbMFYJgwf9Fy3NVntx6HzppTub HEQJTdiPU3VCt3et1C4R9NqJmyG8n8qfyoa3oeEY+LTdIEQTRxgmzVfxMzfOddGQ jlvtwUqzGwSkXiJ/ZpKwFrn2XQiuvRdGeypMZWTk6ZsPAUHUpYvWO4LvhCmMsy1E PErwpHm8XCzOmkcdz2C6c7S9sfg1b8axllzwA5o6forfi9Hu8lk7EK08SRN0SUMf qjBA3upaQ4/HyKOuHMEAnVLErSerUOAM4hpkSt2ua9/KRR7zkx0pzqvAFPAKCuUv jXkYq/PlkbzxglkFiHaVyywAA7UBRPzTBn7NWhAf3XPtfcN5z/pU5qdeLAFRyw/U J77ET0Xq50po16uLIn8MVJY315C+kLvL8uz7IW6vN3koW4ZQeJ+v7s5S5ZZv20CY zLC5N/2loNyOVBvB3mTc+fa+HTDv8B9UBn+gLMHfzuCUbHiDC8BSKk/Z/FtpNCEG lW9whJ/prjZ+VTIiJxbSTg5o8UPl9RAAhDxi6g09BiJe9dBYWdYAe0EenSUllETy jfYeKbo0PG0NcbcsvxapCW1zvarMbczmpNWAe2w4MPuXUj+vfUc= =CAwC -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.13-20180504' into staging ppc patch queue 2018-05-04 Second patch of patches for qemu-2.13 (or whatever the version ends up being called). Highlights are: * Preliminary patches for POWER9 hash MMU support for powernv * A number of cleanups fo pseries startup and LPCR handling * Remove support for explicitly allocated RMAs (which require kernel support that's been gone for 3+ years) * Some mac_newworld cleanups * A few bugfixes # gpg: Signature made Fri 04 May 2018 06:07:43 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.13-20180504: spapr: don't advertise radix GTSE if max-compat-cpu < power9 spapr: don't migrate "spapr_option_vector_ov5_cas" to pre 2.8 machines target/ppc: always set PPC_MEM_TLBIE in pre 2.8 migration hack mac_newworld: move wiring of macio IRQs to macio_newworld_realize() mac_newworld: remove pics IRQ array and wire up macio to OpenPIC directly uninorth: create new uninorth device spapr: Clean up handling of LPCR power-saving exit bits spapr: Move PAPR mode cpu setup fully to spapr code target/ppc: Delay initialization of LPCR_UPRT for secondary cpus spapr: Clean up LPCR updates from hypercalls spapr: Make a helper to set up cpu entry point state spapr: Remove unhelpful helpers from rtas_start_cpu() spapr: Clean up rtas_start_cpu() & rtas_stop_self() target/ppc: Add ppc_store_lpcr() helper spapr: Remove support for explicitly allocated RMAs target/ppc: add basic support for PTCR on POWER9 target/ppc: return a nil HPT base address on sPAPR machines Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
2e4bd4a286
25 changed files with 359 additions and 334 deletions
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@ -71,7 +71,6 @@ typedef struct NewWorldMacIOState {
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/*< public >*/
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OpenPICState *pic;
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qemu_irq irqs[7];
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MACIOIDEState ide[2];
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} NewWorldMacIOState;
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@ -53,4 +53,15 @@ typedef struct UNINHostState {
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MemoryRegion pci_io;
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} UNINHostState;
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typedef struct UNINState {
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SysBusDevice parent_obj;
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MemoryRegion mem;
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int token[1];
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} UNINState;
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#define TYPE_UNI_NORTH "uni-north"
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#define UNI_NORTH(obj) \
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OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH)
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#endif /* UNINORTH_H */
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@ -12,6 +12,7 @@
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#include "hw/qdev.h"
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#include "hw/cpu/core.h"
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#include "target/ppc/cpu-qom.h"
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#include "target/ppc/cpu.h"
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#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
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#define SPAPR_CPU_CORE(obj) \
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@ -38,4 +39,6 @@ typedef struct sPAPRCPUCoreClass {
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} sPAPRCPUCoreClass;
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const char *spapr_get_cpu_core_type(const char *cpu_type);
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void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3);
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#endif
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