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tcg/s390x: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
4944d35910
commit
2e486b5901
1 changed files with 79 additions and 82 deletions
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@ -46,9 +46,7 @@
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/* A scratch register that may be be used throughout the backend. */
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/* A scratch register that may be be used throughout the backend. */
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#define TCG_TMP0 TCG_REG_R1
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#define TCG_TMP0 TCG_REG_R1
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#ifndef CONFIG_SOFTMMU
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#define TCG_GUEST_BASE_REG TCG_REG_R13
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#define TCG_GUEST_BASE_REG TCG_REG_R13
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#endif
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/* All of the following instructions are prefixed with their instruction
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/* All of the following instructions are prefixed with their instruction
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format, and are defined as 8- or 16-bit quantities, even when the two
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format, and are defined as 8- or 16-bit quantities, even when the two
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@ -1768,94 +1766,95 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
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h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
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a_mask = (1 << h->aa.align) - 1;
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a_mask = (1 << h->aa.align) - 1;
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#ifdef CONFIG_SOFTMMU
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if (tcg_use_softmmu) {
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unsigned s_mask = (1 << s_bits) - 1;
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unsigned s_mask = (1 << s_bits) - 1;
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int mem_index = get_mmuidx(oi);
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int mem_index = get_mmuidx(oi);
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int fast_off = tlb_mask_table_ofs(s, mem_index);
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int fast_off = tlb_mask_table_ofs(s, mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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int ofs, a_off;
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int ofs, a_off;
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uint64_t tlb_mask;
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uint64_t tlb_mask;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addr_reg;
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tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off);
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tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off);
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/*
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* For aligned accesses, we check the first byte and include the alignment
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* bits within the address. For unaligned access, we check that we don't
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* cross pages using the address of the last byte of the access.
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*/
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a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask);
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tlb_mask = (uint64_t)s->page_mask | a_mask;
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if (a_off == 0) {
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tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask);
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} else {
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tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off);
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tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask);
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}
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if (is_ld) {
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ofs = offsetof(CPUTLBEntry, addr_read);
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} else {
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ofs = offsetof(CPUTLBEntry, addr_write);
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}
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if (addr_type == TCG_TYPE_I32) {
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ofs += HOST_BIG_ENDIAN * 4;
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tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs);
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} else {
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tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs);
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}
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tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
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ldst->label_ptr[0] = s->code_ptr++;
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h->index = TCG_TMP0;
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tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE,
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offsetof(CPUTLBEntry, addend));
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if (addr_type == TCG_TYPE_I32) {
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tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg);
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h->base = TCG_REG_NONE;
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} else {
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h->base = addr_reg;
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}
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h->disp = 0;
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#else
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if (a_mask) {
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ldst = new_ldst_label(s);
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->oi = oi;
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ldst->addrlo_reg = addr_reg;
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ldst->addrlo_reg = addr_reg;
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/* We are expecting a_bits to max out at 7, much lower than TMLL. */
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tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE,
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tcg_debug_assert(a_mask <= 0xffff);
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s->page_bits - CPU_TLB_ENTRY_BITS);
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tcg_out_insn(s, RI, TMLL, addr_reg, a_mask);
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tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */
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tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off);
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tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off);
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/*
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* For aligned accesses, we check the first byte and include the
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* alignment bits within the address. For unaligned access, we
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* check that we don't cross pages using the address of the last
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* byte of the access.
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*/
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a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask);
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tlb_mask = (uint64_t)s->page_mask | a_mask;
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if (a_off == 0) {
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tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask);
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} else {
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tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off);
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tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask);
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}
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if (is_ld) {
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ofs = offsetof(CPUTLBEntry, addr_read);
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} else {
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ofs = offsetof(CPUTLBEntry, addr_write);
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}
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if (addr_type == TCG_TYPE_I32) {
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ofs += HOST_BIG_ENDIAN * 4;
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tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs);
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} else {
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tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs);
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}
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tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
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ldst->label_ptr[0] = s->code_ptr++;
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ldst->label_ptr[0] = s->code_ptr++;
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}
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h->base = addr_reg;
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h->index = TCG_TMP0;
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if (addr_type == TCG_TYPE_I32) {
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tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE,
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tcg_out_ext32u(s, TCG_TMP0, addr_reg);
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offsetof(CPUTLBEntry, addend));
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h->base = TCG_TMP0;
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}
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if (addr_type == TCG_TYPE_I32) {
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if (guest_base < 0x80000) {
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tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg);
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h->index = TCG_REG_NONE;
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h->base = TCG_REG_NONE;
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h->disp = guest_base;
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} else {
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} else {
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h->base = addr_reg;
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h->index = TCG_GUEST_BASE_REG;
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}
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h->disp = 0;
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h->disp = 0;
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} else {
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if (a_mask) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addr_reg;
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/* We are expecting a_bits to max out at 7, much lower than TMLL. */
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tcg_debug_assert(a_mask <= 0xffff);
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tcg_out_insn(s, RI, TMLL, addr_reg, a_mask);
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tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */
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ldst->label_ptr[0] = s->code_ptr++;
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}
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h->base = addr_reg;
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if (addr_type == TCG_TYPE_I32) {
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tcg_out_ext32u(s, TCG_TMP0, addr_reg);
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h->base = TCG_TMP0;
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}
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if (guest_base < 0x80000) {
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h->index = TCG_REG_NONE;
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h->disp = guest_base;
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} else {
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h->index = TCG_GUEST_BASE_REG;
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h->disp = 0;
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}
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}
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}
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#endif
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return ldst;
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return ldst;
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}
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}
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@ -3453,12 +3452,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
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TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
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CPU_TEMP_BUF_NLONGS * sizeof(long));
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CPU_TEMP_BUF_NLONGS * sizeof(long));
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#ifndef CONFIG_SOFTMMU
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if (!tcg_use_softmmu && guest_base >= 0x80000) {
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if (guest_base >= 0x80000) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
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tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
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tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
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}
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}
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#endif
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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