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target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
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8 changed files with 237 additions and 237 deletions
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@ -20,7 +20,7 @@
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#define ISA_MIPS_R2 0x0000000000000040ULL
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#define ISA_MIPS_R3 0x0000000000000080ULL
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#define ISA_MIPS_R5 0x0000000000000100ULL
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#define ISA_MIPS32R6 0x0000000000002000ULL
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#define ISA_MIPS_R6 0x0000000000000200ULL
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#define ISA_NANOMIPS32 0x0000000000008000ULL
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/*
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* bits 24-39: MIPS ASEs
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@ -85,7 +85,7 @@
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#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
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/* MIPS Technologies "Release 6" */
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#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
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#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
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#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
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/* Wave Computing: "nanoMIPS" */
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