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hw/arm/aspeed_ast27x0 Introduce vbootrom memory region

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Introduce a new vbootrom memory region. The region is mapped at address
"0x00000000" and has a size of 128KB, identical to the SRAM region size.
This memory region is intended for loading a vbootrom image file as part of the
boot process.

The vbootrom registered in the SoC's address space using the ASPEED_DEV_VBOOTROM
index.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250424075135.3715128-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-04-24 15:51:29 +08:00 • committed by Cédric Le Goater
parent af93cef791
commit 2e143da2fb
2 changed files with 11 additions and 0 deletions
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9
hw/arm/aspeed_ast27x0.c
View file

@ -24,6 +24,7 @@
#include "qemu/log.h"
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_VBOOTROM] = 0x00000000,
[ASPEED_DEV_SRAM] = 0x10000000,
[ASPEED_DEV_EHCI1] = 0x12061000,
[ASPEED_DEV_EHCI2] = 0x12063000,
@ -672,6 +673,14 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM], &s->sram);
/* VBOOTROM */
if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
0x20000, errp)) {
return;
}
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;

2
include/hw/arm/aspeed_soc.h
View file

@ -59,6 +59,7 @@ struct AspeedSoCState {
MemoryRegion sram;
MemoryRegion spi_boot_container;
MemoryRegion spi_boot;
MemoryRegion vbootrom;
AddressSpace dram_as;
AspeedRtcState rtc;
AspeedTimerCtrlState timerctrl;
@ -169,6 +170,7 @@ struct AspeedSoCClass {
const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
enum {
ASPEED_DEV_VBOOTROM,
ASPEED_DEV_SPI_BOOT,
ASPEED_DEV_IOMEM,
ASPEED_DEV_UART0,