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https://github.com/Motorhead1991/qemu.git
synced 2025-08-07 09:43:56 -06:00
consistent use of target_ulong and target_phys_addr_t
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@758 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
52c00a5f15
commit
2e12669a4c
5 changed files with 67 additions and 62 deletions
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@ -104,7 +104,7 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
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/* IO ports emulation */
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#define PPC_IO_BASE 0x80000000
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static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr)
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static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value)
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{
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/* Don't polute serial port output */
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#if 0
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@ -121,7 +121,7 @@ static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr)
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cpu_outb(NULL, addr - PPC_IO_BASE, value);
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}
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static uint32_t PPC_io_readb (uint32_t addr)
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static uint32_t PPC_io_readb (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inb(NULL, addr - PPC_IO_BASE);
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@ -141,7 +141,7 @@ static uint32_t PPC_io_readb (uint32_t addr)
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return ret;
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}
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static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr)
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static void PPC_io_writew (target_phys_addr_t addr, uint32_t value)
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{
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if ((addr < 0x800001f0 || addr > 0x800001f7) &&
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(addr < 0x80000170 || addr > 0x80000177)) {
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@ -150,7 +150,7 @@ static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr)
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cpu_outw(NULL, addr - PPC_IO_BASE, value);
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}
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static uint32_t PPC_io_readw (uint32_t addr)
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static uint32_t PPC_io_readw (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inw(NULL, addr - PPC_IO_BASE);
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@ -162,13 +162,13 @@ static uint32_t PPC_io_readw (uint32_t addr)
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return ret;
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}
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static void PPC_io_writel (uint32_t addr, uint32_t value, uint32_t vaddr)
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static void PPC_io_writel (target_phys_addr_t addr, uint32_t value)
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{
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PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, value);
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cpu_outl(NULL, addr - PPC_IO_BASE, value);
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}
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static uint32_t PPC_io_readl (uint32_t addr)
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static uint32_t PPC_io_readl (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inl(NULL, addr - PPC_IO_BASE);
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@ -190,12 +190,12 @@ static CPUReadMemoryFunc *PPC_io_read[] = {
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};
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/* Read-only register (?) */
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static void _PPC_ioB_write (uint32_t addr, uint32_t value, uint32_t vaddr)
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static void _PPC_ioB_write (target_phys_addr_t addr, uint32_t value)
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{
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// printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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}
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static uint32_t _PPC_ioB_read (uint32_t addr)
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static uint32_t _PPC_ioB_read (target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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@ -636,9 +636,9 @@ static void VGA_printf (uint8_t *s)
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for (i = 0; i < format_width; i++) {
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nibble = (arg >> (4 * digit)) & 0x000f;
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if (nibble <= 9)
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PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0', 0);
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PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0');
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else
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PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A', 0);
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PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A');
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digit--;
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}
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in_format = 0;
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@ -647,7 +647,7 @@ static void VGA_printf (uint8_t *s)
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// in_format = 0;
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// }
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} else {
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PPC_io_writeb(PPC_IO_BASE + 0x500, c, 0);
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PPC_io_writeb(PPC_IO_BASE + 0x500, c);
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}
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s++;
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}
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@ -659,10 +659,10 @@ static void VGA_init (void)
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printf("Init VGA...\n");
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#if 1
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/* switch to color mode and enable CPU access 480 lines */
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PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3, 0);
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PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3);
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/* more than 64k 3C4/04 */
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PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04, 0);
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PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02, 0);
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PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04);
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PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02);
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#endif
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VGA_printf("PPC VGA BIOS...\n");
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}
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@ -690,7 +690,7 @@ void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size,
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{
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#if 1
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uint32_t offset =
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*((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
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*((uint32_t *)(phys_ram_base + kernel_addr));
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#else
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uint32_t offset = 12;
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#endif
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@ -816,7 +816,7 @@ void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size,
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{
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#if 0
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uint32_t offset =
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*((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
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*((uint32_t *)(phys_ram_base + kernel_addr));
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#else
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uint32_t offset = 12;
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#endif
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12
hw/vga.c
12
hw/vga.c
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@ -648,7 +648,7 @@ static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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#endif
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/* called for accesses between 0xa0000 and 0xc0000 */
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static uint32_t vga_mem_readb(uint32_t addr)
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static uint32_t vga_mem_readb(target_phys_addr_t addr)
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{
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VGAState *s = &vga_state;
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int memory_map_mode, plane;
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@ -704,7 +704,7 @@ static uint32_t vga_mem_readb(uint32_t addr)
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return ret;
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}
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static uint32_t vga_mem_readw(uint32_t addr)
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static uint32_t vga_mem_readw(target_phys_addr_t addr)
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{
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uint32_t v;
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v = vga_mem_readb(addr);
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@ -712,7 +712,7 @@ static uint32_t vga_mem_readw(uint32_t addr)
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return v;
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}
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static uint32_t vga_mem_readl(uint32_t addr)
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static uint32_t vga_mem_readl(target_phys_addr_t addr)
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{
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uint32_t v;
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v = vga_mem_readb(addr);
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@ -723,7 +723,7 @@ static uint32_t vga_mem_readl(uint32_t addr)
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}
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/* called for accesses between 0xa0000 and 0xc0000 */
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static void vga_mem_writeb(uint32_t addr, uint32_t val)
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static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val)
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{
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VGAState *s = &vga_state;
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int memory_map_mode, plane, write_mode, b, func_select;
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@ -851,13 +851,13 @@ static void vga_mem_writeb(uint32_t addr, uint32_t val)
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}
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}
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static void vga_mem_writew(uint32_t addr, uint32_t val)
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static void vga_mem_writew(target_phys_addr_t addr, uint32_t val)
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{
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vga_mem_writeb(addr, val & 0xff);
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vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
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}
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static void vga_mem_writel(uint32_t addr, uint32_t val)
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static void vga_mem_writel(target_phys_addr_t addr, uint32_t val)
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{
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vga_mem_writeb(addr, val & 0xff);
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vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
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