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target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu

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riscv_cpu_do_interrupt() is not reachable on user emulation.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230626232007.8933-7-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-06-27 00:19:30 +02:00
parent 14482b1360
commit 2dd3174990
2 changed files with 5 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

5
target/riscv/cpu.h
View file

@ -484,7 +484,6 @@ extern const char * const riscv_int_regnamesh[];
extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_fpr_regnames[];
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s); int cpuid, DumpState *s);
int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
@ -514,6 +513,7 @@ int riscv_cpu_max_xlen(RISCVCPUClass *mcc);
bool riscv_cpu_option_set(const char *optname); bool riscv_cpu_option_set(const char *optname);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
void riscv_cpu_do_interrupt(CPUState *cpu);
void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename);
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size, vaddr addr, unsigned size,
@ -539,7 +539,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
void *rmw_fn_arg); void *rmw_fn_arg);
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
#endif #endif /* !CONFIG_USER_ONLY */
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(void); void riscv_translate_init(void);

7
target/riscv/cpu_helper.c
View file

@ -1635,7 +1635,6 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
return xinsn; return xinsn;
} }
#endif /* !CONFIG_USER_ONLY */
/* /*
* Handle Traps * Handle Traps
@ -1645,8 +1644,6 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
*/ */
void riscv_cpu_do_interrupt(CPUState *cs) void riscv_cpu_do_interrupt(CPUState *cs)
{ {
#if !defined(CONFIG_USER_ONLY)
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
bool write_gva = false; bool write_gva = false;
@ -1842,6 +1839,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->two_stage_lookup = false; env->two_stage_lookup = false;
env->two_stage_indirect_lookup = false; env->two_stage_indirect_lookup = false;
#endif
cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
} }
#endif /* !CONFIG_USER_ONLY */