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target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)

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Convert 3-register floating-point or fixed-point operations
to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-20-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 10:37:13 +02:00
parent ff29e5d3c0
commit 2d5246f305
2 changed files with 76 additions and 176 deletions
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39
target/mips/tcg/msa.decode
View file

@ -23,6 +23,7 @@
%bit_m 16:7 !function=bit_m
%2r_df_w 16:1 !function=plus_2
%3r_df_h 21:1 !function=plus_1
%3r_df_w 21:1 !function=plus_2
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
@ -32,6 +33,7 @@
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w
@3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h
@3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i
@ -86,9 +88,46 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w
FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w
FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w
FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w
FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w
FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w
FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w
FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w
FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w
FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w
FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w
FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w
FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w
FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w
FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w
FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w
FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w
FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w
FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w
FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w
FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w
FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w
FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w
FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w
FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w
FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w
FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w
FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w
FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w
FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w
MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h
MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h
MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h
FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w
FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w
FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w
MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h
MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h
MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h