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hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes

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RISCV_IOMMU_REG_IOCOUNTINH is done by riscv_iommu_process_iocntinh_cy(),
which is called during riscv_iommu_mmio_write() callback via a new
riscv_iommu_pricess_hpm_writes() helper.

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250224190826.1858473-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Tomasz Jeznach 2025-02-24 16:08:21 -03:00 • committed by Alistair Francis
parent ffb37df056
commit 2cf2a6c027
3 changed files with 99 additions and 0 deletions
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38
hw/riscv/riscv-iommu.c
View file

@ -2024,6 +2024,27 @@ static void riscv_iommu_update_ipsr(RISCVIOMMUState *s, uint64_t data)
riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IPSR, ipsr_set, ipsr_clr);
}
static void riscv_iommu_process_hpm_writes(RISCVIOMMUState *s,
uint32_t regb,
bool prev_cy_inh)
{
switch (regb) {
case RISCV_IOMMU_REG_IOCOUNTINH:
riscv_iommu_process_iocntinh_cy(s, prev_cy_inh);
break;
case RISCV_IOMMU_REG_IOHPMCYCLES:
case RISCV_IOMMU_REG_IOHPMCYCLES + 4:
/* not yet implemented */
break;
case RISCV_IOMMU_REG_IOHPMEVT_BASE ...
RISCV_IOMMU_REG_IOHPMEVT(RISCV_IOMMU_IOCOUNT_NUM) + 4:
/* not yet implemented */
break;
}
}
/*
* Write the resulting value of 'data' for the reg specified
* by 'reg_addr', after considering read-only/read-write/write-clear
@ -2051,6 +2072,7 @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
uint32_t regb = addr & ~3;
uint32_t busy = 0;
uint64_t val = 0;
bool cy_inh = false;
if ((addr & (size - 1)) != 0) {
/* Unsupported MMIO alignment or access size */
@ -2118,6 +2140,16 @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
busy = RISCV_IOMMU_TR_REQ_CTL_GO_BUSY;
break;
case RISCV_IOMMU_REG_IOCOUNTINH:
if (addr != RISCV_IOMMU_REG_IOCOUNTINH) {
break;
}
/* Store previous value of CY bit. */
cy_inh = !!(riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTINH) &
RISCV_IOMMU_IOCOUNTINH_CY);
break;
default:
break;
}
@ -2136,6 +2168,12 @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
stl_le_p(&s->regs_rw[regb], rw | busy);
}
/* Process HPM writes and update any internal state if needed. */
if (regb >= RISCV_IOMMU_REG_IOCOUNTOVF &&
regb <= (RISCV_IOMMU_REG_IOHPMEVT(RISCV_IOMMU_IOCOUNT_NUM) + 4)) {
riscv_iommu_process_hpm_writes(s, regb, cy_inh);
}
if (process_fn) {
process_fn(s);
}