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https://github.com/Motorhead1991/qemu.git
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Support for address masking
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4882 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
a5a52cf246
commit
2cade6a3f6
3 changed files with 58 additions and 33 deletions
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@ -57,6 +57,7 @@ typedef struct DisasContext {
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int is_br;
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int mem_idx;
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int fpu_enabled;
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int address_mask_32bit;
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struct TranslationBlock *tb;
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uint32_t features;
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} DisasContext;
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@ -201,11 +202,21 @@ static void gen_op_store_QT0_fpr(unsigned int dst)
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#endif
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#endif
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#ifdef TARGET_ABI32
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#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
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#ifdef TARGET_SPARC64
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#ifndef TARGET_ABI32
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#define AM_CHECK(dc) ((dc)->address_mask_32bit)
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#else
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#define ABI32_MASK(addr)
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#define AM_CHECK(dc) (1)
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#endif
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#endif
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static inline void gen_address_mask(DisasContext *dc, TCGv addr)
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{
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#ifdef TARGET_SPARC64
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if (AM_CHECK(dc))
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tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
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#endif
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}
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static inline void gen_movl_reg_TN(int reg, TCGv tn)
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{
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@ -4199,15 +4210,15 @@ static void disas_sparc_insn(DisasContext * dc)
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(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
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switch (xop) {
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case 0x0: /* load unsigned word */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x1: /* load unsigned byte */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x2: /* load unsigned halfword */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x3: /* load double word */
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@ -4221,7 +4232,7 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_gen_helper_0_2(helper_check_align, cpu_addr,
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r_const); // XXX remove
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tcg_temp_free(r_const);
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
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tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
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tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
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@ -4232,18 +4243,18 @@ static void disas_sparc_insn(DisasContext * dc)
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}
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break;
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case 0x9: /* load signed byte */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0xa: /* load signed halfword */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0xd: /* ldstub -- XXX: should be atomically */
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{
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TCGv r_const;
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
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r_const = tcg_const_tl(0xff);
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tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
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@ -4254,7 +4265,7 @@ static void disas_sparc_insn(DisasContext * dc)
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atomically */
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CHECK_IU_FEATURE(dc, SWAP);
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gen_movl_reg_TN(rd, cpu_val);
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
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tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
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tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
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@ -4356,11 +4367,11 @@ static void disas_sparc_insn(DisasContext * dc)
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#endif
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#ifdef TARGET_SPARC64
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case 0x08: /* V9 ldsw */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x0b: /* V9 ldx */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x18: /* V9 ldswa */
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@ -4402,13 +4413,13 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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switch (xop) {
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case 0x20: /* load fpreg */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
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tcg_gen_st_i32(cpu_tmp32, cpu_env,
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offsetof(CPUState, fpr[rd]));
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break;
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case 0x21: /* load fsr */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
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tcg_gen_st_i32(cpu_tmp32, cpu_env,
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offsetof(CPUState, ft0));
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@ -4443,15 +4454,15 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_movl_reg_TN(rd, cpu_val);
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switch (xop) {
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case 0x4: /* store word */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x5: /* store byte */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x6: /* store halfword */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x7: /* store double word */
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@ -4461,7 +4472,7 @@ static void disas_sparc_insn(DisasContext * dc)
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TCGv r_low, r_const;
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save_state(dc, cpu_cond);
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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r_const = tcg_const_i32(7);
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tcg_gen_helper_0_2(helper_check_align, cpu_addr,
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r_const); // XXX remove
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@ -4522,7 +4533,7 @@ static void disas_sparc_insn(DisasContext * dc)
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#endif
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#ifdef TARGET_SPARC64
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case 0x0e: /* V9 stx */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x1e: /* V9 stxa */
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@ -4539,13 +4550,13 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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switch (xop) {
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case 0x24: /* store fpreg */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_ld_i32(cpu_tmp32, cpu_env,
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offsetof(CPUState, fpr[rd]));
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tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
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break;
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case 0x25: /* stfsr, V9 stxfsr */
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ABI32_MASK(cpu_addr);
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gen_address_mask(dc, cpu_addr);
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tcg_gen_helper_0_0(helper_stfsr);
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tcg_gen_ld_i32(cpu_tmp32, cpu_env,
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offsetof(CPUState, ft0));
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@ -4739,6 +4750,9 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
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#endif
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} else
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dc->fpu_enabled = 0;
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#ifdef TARGET_SPARC64
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dc->address_mask_32bit = env->pstate & PS_AM;
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#endif
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gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
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cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
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