motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 16:23:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

memory: add owner argument to initialization functions

Browse source 
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2013-06-06 05:41:28 -04:00
parent 5767e4e198
commit 2c9b15cab1
319 changed files with 787 additions and 759 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/intc/apic.c
View file

@ -873,7 +873,7 @@ static const MemoryRegionOps apic_io_ops = {
static void apic_init(APICCommonState *s)
{
memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic-msi",
memory_region_init_io(&s->io_memory, NULL, &apic_io_ops, s, "apic-msi",
APIC_SPACE_SIZE);
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);

6
hw/intc/arm_gic.c
View file

@ -656,7 +656,7 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq)
for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
memory_region_init_io(&s->iomem, NULL, &gic_dist_ops, s, "gic_dist", 0x1000);
}
static void arm_gic_realize(DeviceState *dev, Error **errp)
@ -682,11 +682,11 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
* GIC v2 defines a larger memory region (0x1000) so this will need
* to be extended when we implement A15.
*/
memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
memory_region_init_io(&s->cpuiomem[0], NULL, &gic_thiscpu_ops, s,
"gic_cpu", 0x100);
for (i = 0; i < NUM_CPU(s); i++) {
s->backref[i] = s;
memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
memory_region_init_io(&s->cpuiomem[i+1], NULL, &gic_cpu_ops, &s->backref[i],
"gic_cpu", 0x100);
}
/* Distributor */

4
hw/intc/arm_gic_kvm.c
View file

@ -120,7 +120,7 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
sysbus_init_irq(sbd, &s->parent_irq[i]);
}
/* Distributor */
memory_region_init_reservation(&s->iomem, "kvm-gic_dist", 0x1000);
memory_region_init_reservation(&s->iomem, NULL, "kvm-gic_dist", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
kvm_arm_register_device(&s->iomem,
(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
@ -129,7 +129,7 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
* provide the "interface for core #N" memory regions, because
* cores with a VGIC don't have those.
*/
memory_region_init_reservation(&s->cpuiomem[0], "kvm-gic_cpu", 0x1000);
memory_region_init_reservation(&s->cpuiomem[0], NULL, "kvm-gic_cpu", 0x1000);
sysbus_init_mmio(sbd, &s->cpuiomem[0]);
kvm_arm_register_device(&s->cpuiomem[0],
(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)

6
hw/intc/armv7m_nvic.c
View file

@ -487,17 +487,17 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
* We use overlaying to put the GIC like registers
* over the top of the system control register region.
*/
memory_region_init(&s->container, "nvic", 0x1000);
memory_region_init(&s->container, NULL, "nvic", 0x1000);
/* The system register region goes at the bottom of the priority
* stack as it covers the whole page.
*/
memory_region_init_io(&s->sysregmem, &nvic_sysreg_ops, s,
memory_region_init_io(&s->sysregmem, NULL, &nvic_sysreg_ops, s,
"nvic_sysregs", 0x1000);
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
/* Alias the GIC region so we can get only the section of it
* we need, and layer it on top of the system register region.
*/
memory_region_init_alias(&s->gic_iomem_alias, "nvic-gic", &s->gic.iomem,
memory_region_init_alias(&s->gic_iomem_alias, NULL, "nvic-gic", &s->gic.iomem,
0x100, 0xc00);
memory_region_add_subregion_overlap(&s->container, 0x100,
&s->gic_iomem_alias, 1);

2
hw/intc/etraxfs_pic.c
View file

@ -146,7 +146,7 @@ static int etraxfs_pic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_nmi);
memory_region_init_io(&s->mmio, &pic_ops, s, "etraxfs-pic", R_MAX * 4);
memory_region_init_io(&s->mmio, NULL, &pic_ops, s, "etraxfs-pic", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
return 0;
}

2
hw/intc/exynos4210_combiner.c
View file

@ -417,7 +417,7 @@ static int exynos4210_combiner_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->output_irq[i]);
}
memory_region_init_io(&s->iomem, &exynos4210_combiner_ops, s,
memory_region_init_io(&s->iomem, NULL, &exynos4210_combiner_ops, s,
"exynos4210-combiner", IIC_REGION_SIZE);
sysbus_init_mmio(dev, &s->iomem);

8
hw/intc/exynos4210_gic.c
View file

@ -299,15 +299,15 @@ static int exynos4210_gic_init(SysBusDevice *dev)
qdev_init_gpio_in(&s->busdev.qdev, exynos4210_gic_set_irq,
EXYNOS4210_GIC_NIRQ - 32);
memory_region_init(&s->cpu_container, "exynos4210-cpu-container",
memory_region_init(&s->cpu_container, NULL, "exynos4210-cpu-container",
EXYNOS4210_EXT_GIC_CPU_REGION_SIZE);
memory_region_init(&s->dist_container, "exynos4210-dist-container",
memory_region_init(&s->dist_container, NULL, "exynos4210-dist-container",
EXYNOS4210_EXT_GIC_DIST_REGION_SIZE);
for (i = 0; i < s->num_cpu; i++) {
/* Map CPU interface per SMP Core */
sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
memory_region_init_alias(&s->cpu_alias[i],
memory_region_init_alias(&s->cpu_alias[i], NULL,
cpu_alias_name,
sysbus_mmio_get_region(busdev, 1),
0,
@ -317,7 +317,7 @@ static int exynos4210_gic_init(SysBusDevice *dev)
/* Map Distributor per SMP Core */
sprintf(dist_alias_name, "%s%x", dist_prefix, i);
memory_region_init_alias(&s->dist_alias[i],
memory_region_init_alias(&s->dist_alias[i], NULL,
dist_alias_name,
sysbus_mmio_get_region(busdev, 0),
0,

2
hw/intc/grlib_irqmp.c
View file

@ -344,7 +344,7 @@ static int grlib_irqmp_init(SysBusDevice *dev)
return -1;
}
memory_region_init_io(&irqmp->iomem, &grlib_irqmp_ops, irqmp,
memory_region_init_io(&irqmp->iomem, NULL, &grlib_irqmp_ops, irqmp,
"irqmp", IRQMP_REG_SIZE);
irqmp->state = g_malloc0(sizeof *irqmp->state);

2
hw/intc/heathrow_pic.c
View file

@ -205,7 +205,7 @@ qemu_irq *heathrow_pic_init(MemoryRegion **pmem,
s = g_malloc0(sizeof(HeathrowPICS));
/* only 1 CPU */
s->irqs = irqs[0];
memory_region_init_io(&s->mem, &heathrow_pic_ops, s,
memory_region_init_io(&s->mem, NULL, &heathrow_pic_ops, s,
"heathrow-pic", 0x1000);
*pmem = &s->mem;

4
hw/intc/i8259.c
View file

@ -417,8 +417,8 @@ static void pic_realize(DeviceState *dev, Error **err)
PICCommonState *s = PIC_COMMON(dev);
PICClass *pc = PIC_GET_CLASS(dev);
memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
memory_region_init_io(&s->base_io, NULL, &pic_base_ioport_ops, s, "pic", 2);
memory_region_init_io(&s->elcr_io, NULL, &pic_elcr_ioport_ops, s, "elcr", 1);
qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out));
qdev_init_gpio_in(dev, pic_set_irq, 8);

2
hw/intc/imx_avic.c
View file

@ -372,7 +372,7 @@ static int imx_avic_init(SysBusDevice *dev)
{
IMXAVICState *s = FROM_SYSBUS(IMXAVICState, dev);
memory_region_init_io(&s->iomem, &imx_avic_ops, s, "imx_avic", 0x1000);
memory_region_init_io(&s->iomem, NULL, &imx_avic_ops, s, "imx_avic", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);

2
hw/intc/ioapic.c
View file

@ -227,7 +227,7 @@ static const MemoryRegionOps ioapic_io_ops = {
static void ioapic_init(IOAPICCommonState *s, int instance_no)
{
memory_region_init_io(&s->io_memory, &ioapic_io_ops, s, "ioapic", 0x1000);
memory_region_init_io(&s->io_memory, NULL, &ioapic_io_ops, s, "ioapic", 0x1000);
qdev_init_gpio_in(&s->busdev.qdev, ioapic_set_irq, IOAPIC_NUM_PINS);

4
hw/intc/omap_intc.c
View file

@ -367,7 +367,7 @@ static int omap_intc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_intr[0]);
sysbus_init_irq(dev, &s->parent_intr[1]);
qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s,
memory_region_init_io(&s->mmio, NULL, &omap_inth_mem_ops, s,
"omap-intc", s->size);
sysbus_init_mmio(dev, &s->mmio);
return 0;
@ -609,7 +609,7 @@ static int omap2_intc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_intr[0]);
sysbus_init_irq(dev, &s->parent_intr[1]);
qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s,
memory_region_init_io(&s->mmio, NULL, &omap2_inth_mem_ops, s,
"omap2-intc", 0x1000);
sysbus_init_mmio(dev, &s->mmio);
return 0;

4
hw/intc/openpic.c
View file

@ -1516,7 +1516,7 @@ static void map_list(OpenPICState *opp, const MemReg *list, int *count)
while (list->name) {
assert(*count < ARRAY_SIZE(opp->sub_io_mem));
memory_region_init_io(&opp->sub_io_mem[*count], list->ops, opp,
memory_region_init_io(&opp->sub_io_mem[*count], NULL, list->ops, opp,
list->name, list->size);
memory_region_add_subregion(&opp->mem, list->start_addr,
@ -1531,7 +1531,7 @@ static void openpic_init(Object *obj)
{
OpenPICState *opp = OPENPIC(obj);
memory_region_init(&opp->mem, "openpic", 0x40000);
memory_region_init(&opp->mem, NULL, "openpic", 0x40000);
}
static void openpic_realize(DeviceState *dev, Error **errp)

2
hw/intc/openpic_kvm.c
View file

@ -155,7 +155,7 @@ static void kvm_openpic_init(Object *obj)
{
KVMOpenPICState *opp = KVM_OPENPIC(obj);
memory_region_init_io(&opp->mem, &kvm_openpic_mem_ops, opp,
memory_region_init_io(&opp->mem, NULL, &kvm_openpic_mem_ops, opp,
"kvm-openpic", 0x40000);
}

2
hw/intc/pl190.c
View file

@ -236,7 +236,7 @@ static int pl190_init(SysBusDevice *dev)
{
pl190_state *s = FROM_SYSBUS(pl190_state, dev);
memory_region_init_io(&s->iomem, &pl190_ops, s, "pl190", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pl190_ops, s, "pl190", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
sysbus_init_irq(dev, &s->irq);

2
hw/intc/puv3_intc.c
View file

@ -106,7 +106,7 @@ static int puv3_intc_init(SysBusDevice *dev)
s->reg_ICMR = 0;
s->reg_ICPR = 0;
memory_region_init_io(&s->iomem, &puv3_intc_ops, s, "puv3_intc",
memory_region_init_io(&s->iomem, NULL, &puv3_intc_ops, s, "puv3_intc",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);

2
hw/intc/realview_gic.c
View file

@ -43,7 +43,7 @@ static int realview_gic_init(SysBusDevice *dev)
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, realview_gic_set_irq, numirq - 32);
memory_region_init(&s->container, "realview-gic-container", 0x2000);
memory_region_init(&s->container, NULL, "realview-gic-container", 0x2000);
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(busdev, 1));
memory_region_add_subregion(&s->container, 0x1000,

6
hw/intc/sh_intc.c
View file

@ -319,11 +319,11 @@ static unsigned int sh_intc_register(MemoryRegion *sysmem,
#define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s"
snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "p4");
memory_region_init_alias(iomem_p4, name, iomem, INTC_A7(address), 4);
memory_region_init_alias(iomem_p4, NULL, name, iomem, INTC_A7(address), 4);
memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "a7");
memory_region_init_alias(iomem_a7, name, iomem, INTC_A7(address), 4);
memory_region_init_alias(iomem_a7, NULL, name, iomem, INTC_A7(address), 4);
memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
#undef SH_INTC_IOMEM_FORMAT
@ -466,7 +466,7 @@ int sh_intc_init(MemoryRegion *sysmem,
desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
memory_region_init_io(&desc->iomem, &sh_intc_ops, desc,
memory_region_init_io(&desc->iomem, NULL, &sh_intc_ops, desc,
"interrupt-controller", 0x100000000ULL);
#define INT_REG_PARAMS(reg_struct, type, action, j) \

4
hw/intc/slavio_intctl.c
View file

@ -426,7 +426,7 @@ static int slavio_intctl_init1(SysBusDevice *dev)
char slave_name[45];
qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
memory_region_init_io(&s->iomem, &slavio_intctlm_mem_ops, s,
memory_region_init_io(&s->iomem, NULL, &slavio_intctlm_mem_ops, s,
"master-interrupt-controller", INTCTLM_SIZE);
sysbus_init_mmio(dev, &s->iomem);
@ -436,7 +436,7 @@ static int slavio_intctl_init1(SysBusDevice *dev)
for (j = 0; j < MAX_PILS; j++) {
sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
}
memory_region_init_io(&s->slaves[i].iomem, &slavio_intctl_mem_ops,
memory_region_init_io(&s->slaves[i].iomem, NULL, &slavio_intctl_mem_ops,
&s->slaves[i], slave_name, INTCTL_SIZE);
sysbus_init_mmio(dev, &s->slaves[i].iomem);
s->slaves[i].cpu = i;

2
hw/intc/xilinx_intc.c
View file

@ -160,7 +160,7 @@ static int xilinx_intc_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
sysbus_init_irq(dev, &p->parent_irq);
memory_region_init_io(&p->mmio, &pic_ops, p, "xlnx.xps-intc", R_MAX * 4);
memory_region_init_io(&p->mmio, NULL, &pic_ops, p, "xlnx.xps-intc", R_MAX * 4);
sysbus_init_mmio(dev, &p->mmio);
return 0;
}