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target/ppc: Implement vsldbi/vsrdbi instructions

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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-5-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Matheus Ferst 2021-11-04 09:36:58 -03:00 • committed by David Gibson
parent 00a16569eb
commit 2c716b4da5
2 changed files with 74 additions and 0 deletions
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8
target/ppc/insn32.decode
View file

@ -38,6 +38,9 @@
%dx_d 6:s10 16:5 0:1 %dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d @DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
&VN vrt vra vrb sh
@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
&VX vrt vra vrb &VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX @VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
@ -338,3 +341,8 @@ VCLZDM 000100 ..... ..... ..... 11110000100 @VX
VCTZDM 000100 ..... ..... ..... 11111000100 @VX VCTZDM 000100 ..... ..... ..... 11111000100 @VX
VPDEPD 000100 ..... ..... ..... 10111001101 @VX VPDEPD 000100 ..... ..... ..... 10111001101 @VX
VPEXTD 000100 ..... ..... ..... 10110001101 @VX VPEXTD 000100 ..... ..... ..... 10110001101 @VX
## Vector Permute and Formatting Instruction
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN

66
target/ppc/translate/vmx-impl.c.inc
View file

@ -1257,6 +1257,72 @@ static void gen_vsldoi(DisasContext *ctx)
tcg_temp_free_i32(sh); tcg_temp_free_i32(sh);
} }
static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a)
{
TCGv_i64 t0, t1, t2;
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
get_avr64(t0, a->vra, true);
get_avr64(t1, a->vra, false);
if (a->sh != 0) {
t2 = tcg_temp_new_i64();
get_avr64(t2, a->vrb, true);
tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh);
tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh);
tcg_temp_free_i64(t2);
}
set_avr64(a->vrt, t0, true);
set_avr64(a->vrt, t1, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
return true;
}
static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
{
TCGv_i64 t2, t1, t0;
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
get_avr64(t0, a->vrb, false);
get_avr64(t1, a->vrb, true);
if (a->sh != 0) {
t2 = tcg_temp_new_i64();
get_avr64(t2, a->vra, false);
tcg_gen_extract2_i64(t0, t0, t1, a->sh);
tcg_gen_extract2_i64(t1, t1, t2, a->sh);
tcg_temp_free_i64(t2);
}
set_avr64(a->vrt, t0, false);
set_avr64(a->vrt, t1, true);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
return true;
}
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \ #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \ { \