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target/arm: Convert Neon one-register-and-immediate insns to decodetree

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Convert the insns in the one-register-and-immediate group to decodetree.

In the new decode, our asimd_imm_const() function returns a 64-bit value
rather than a 32-bit one, which means we don't need to treat cmode=14 op=1
as a special case in the decoder (it is the only encoding where the two
halves of the 64-bit value are different).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-10-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-05-22 15:55:20 +01:00
parent 3da26f1171
commit 2c35a39eda
3 changed files with 142 additions and 99 deletions
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101
target/arm/translate.c
View file

@ -5232,105 +5232,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
/* Three register same length: handled by decodetree */
return 1;
} else if (insn & (1 << 4)) {
if ((insn & 0x00380080) != 0) {
/* Two registers and shift: handled by decodetree */
return 1;
} else { /* (insn & 0x00380080) == 0 */
int invert, reg_ofs, vec_size;
if (q && (rd & 1)) {
return 1;
}
op = (insn >> 8) & 0xf;
/* One register and immediate. */
imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
invert = (insn & (1 << 5)) != 0;
/* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
* We choose to not special-case this and will behave as if a
* valid constant encoding of 0 had been given.
*/
switch (op) {
case 0: case 1:
/* no-op */
break;
case 2: case 3:
imm <<= 8;
break;
case 4: case 5:
imm <<= 16;
break;
case 6: case 7:
imm <<= 24;
break;
case 8: case 9:
imm |= imm << 16;
break;
case 10: case 11:
imm = (imm << 8) | (imm << 24);
break;
case 12:
imm = (imm << 8) | 0xff;
break;
case 13:
imm = (imm << 16) | 0xffff;
break;
case 14:
imm |= (imm << 8) | (imm << 16) | (imm << 24);
if (invert) {
imm = ~imm;
}
break;
case 15:
if (invert) {
return 1;
}
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
break;
}
if (invert) {
imm = ~imm;
}
reg_ofs = neon_reg_offset(rd, 0);
vec_size = q ? 16 : 8;
if (op & 1 && op < 12) {
if (invert) {
/* The immediate value has already been inverted,
* so BIC becomes AND.
*/
tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,
vec_size, vec_size);
} else {
tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,
vec_size, vec_size);
}
} else {
/* VMOV, VMVN. */
if (op == 14 && invert) {
TCGv_i64 t64 = tcg_temp_new_i64();
for (pass = 0; pass <= q; ++pass) {
uint64_t val = 0;
int n;
for (n = 0; n < 8; n++) {
if (imm & (1 << (n + pass * 8))) {
val |= 0xffull << (n * 8);
}
}
tcg_gen_movi_i64(t64, val);
neon_store_reg64(t64, rd + pass);
}
tcg_temp_free_i64(t64);
} else {
tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size,
vec_size, imm);
}
}
}
/* Two registers and shift or reg and imm: handled by decodetree */
return 1;
} else { /* (insn & 0x00800010 == 0x00800000) */
if (size != 3) {
op = (insn >> 8) & 0xf;