mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-02 15:23:53 -06:00
exec: Make ldq/ldub_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
parent
fdfba1a298
commit
2c17449b30
25 changed files with 184 additions and 136 deletions
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@ -105,7 +105,7 @@ static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
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unsigned int flags;
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sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
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sc->base = ldq_phys(addr + offsetof(struct vmcb_seg, base));
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sc->base = ldq_phys(cs->as, addr + offsetof(struct vmcb_seg, base));
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sc->limit = ldl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit));
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flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
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sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
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@ -178,7 +178,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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/* load the interception bitmaps so we do not need to access the
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vmcb in svm mode */
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env->intercept = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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env->intercept = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
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control.intercept));
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env->intercept_cr_read = lduw_phys(env->vm_vmcb +
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offsetof(struct vmcb,
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@ -200,15 +200,15 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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/* enable intercepts */
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env->hflags |= HF_SVMI_MASK;
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env->tsc_offset = ldq_phys(env->vm_vmcb +
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env->tsc_offset = ldq_phys(cs->as, env->vm_vmcb +
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offsetof(struct vmcb, control.tsc_offset));
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env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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env->gdt.base = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
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save.gdtr.base));
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env->gdt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
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save.gdtr.limit));
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env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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env->idt.base = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
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save.idtr.base));
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env->idt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
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save.idtr.limit));
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@ -216,13 +216,17 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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/* clear exit_info_2 so we behave like the real hardware */
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stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
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cpu_x86_update_cr0(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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cpu_x86_update_cr0(env, ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb,
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save.cr0)));
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cpu_x86_update_cr4(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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cpu_x86_update_cr4(env, ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb,
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save.cr4)));
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cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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cpu_x86_update_cr3(env, ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb,
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save.cr3)));
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env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2));
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env->cr[2] = ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, save.cr2));
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int_ctl = ldl_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
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env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);
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@ -235,9 +239,11 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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}
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cpu_load_efer(env,
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ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer)));
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ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, save.efer)));
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env->eflags = 0;
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cpu_load_eflags(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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cpu_load_eflags(env, ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb,
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save.rflags)),
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~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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CC_OP = CC_OP_EFLAGS;
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@ -251,18 +257,25 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
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R_DS);
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env->eip = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
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env->eip = ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, save.rip));
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env->regs[R_ESP] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
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env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
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env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
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env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
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cpu_x86_set_cpl(env, ldub_phys(env->vm_vmcb + offsetof(struct vmcb,
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env->regs[R_ESP] = ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, save.rsp));
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env->regs[R_EAX] = ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, save.rax));
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env->dr[7] = ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, save.dr7));
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env->dr[6] = ldq_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, save.dr6));
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cpu_x86_set_cpl(env, ldub_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb,
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save.cpl)));
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/* FIXME: guest state consistency checks */
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switch (ldub_phys(env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
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switch (ldub_phys(cs->as,
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env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
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case TLB_CONTROL_DO_NOTHING:
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break;
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case TLB_CONTROL_FLUSH_ALL_ASID:
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@ -339,6 +352,7 @@ void helper_vmmcall(CPUX86State *env)
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void helper_vmload(CPUX86State *env, int aflag)
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{
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CPUState *cs = ENV_GET_CPU(env);
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target_ulong addr;
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0);
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@ -351,7 +365,7 @@ void helper_vmload(CPUX86State *env, int aflag)
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx
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"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, ldq_phys(addr + offsetof(struct vmcb,
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addr, ldq_phys(cs->as, addr + offsetof(struct vmcb,
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save.fs.base)),
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env->segs[R_FS].base);
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@ -361,22 +375,24 @@ void helper_vmload(CPUX86State *env, int aflag)
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svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt);
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#ifdef TARGET_X86_64
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env->kernelgsbase = ldq_phys(addr + offsetof(struct vmcb,
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env->kernelgsbase = ldq_phys(cs->as, addr + offsetof(struct vmcb,
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save.kernel_gs_base));
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env->lstar = ldq_phys(addr + offsetof(struct vmcb, save.lstar));
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env->cstar = ldq_phys(addr + offsetof(struct vmcb, save.cstar));
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env->fmask = ldq_phys(addr + offsetof(struct vmcb, save.sfmask));
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env->lstar = ldq_phys(cs->as, addr + offsetof(struct vmcb, save.lstar));
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env->cstar = ldq_phys(cs->as, addr + offsetof(struct vmcb, save.cstar));
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env->fmask = ldq_phys(cs->as, addr + offsetof(struct vmcb, save.sfmask));
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#endif
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env->star = ldq_phys(addr + offsetof(struct vmcb, save.star));
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env->sysenter_cs = ldq_phys(addr + offsetof(struct vmcb, save.sysenter_cs));
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env->sysenter_esp = ldq_phys(addr + offsetof(struct vmcb,
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env->star = ldq_phys(cs->as, addr + offsetof(struct vmcb, save.star));
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env->sysenter_cs = ldq_phys(cs->as,
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addr + offsetof(struct vmcb, save.sysenter_cs));
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env->sysenter_esp = ldq_phys(cs->as, addr + offsetof(struct vmcb,
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save.sysenter_esp));
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env->sysenter_eip = ldq_phys(addr + offsetof(struct vmcb,
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env->sysenter_eip = ldq_phys(cs->as, addr + offsetof(struct vmcb,
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save.sysenter_eip));
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}
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void helper_vmsave(CPUX86State *env, int aflag)
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{
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CPUState *cs = ENV_GET_CPU(env);
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target_ulong addr;
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0);
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@ -389,7 +405,8 @@ void helper_vmsave(CPUX86State *env, int aflag)
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx
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"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, ldq_phys(addr + offsetof(struct vmcb, save.fs.base)),
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addr, ldq_phys(cs->as,
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addr + offsetof(struct vmcb, save.fs.base)),
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env->segs[R_FS].base);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.fs),
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@ -455,6 +472,8 @@ void helper_invlpga(CPUX86State *env, int aflag)
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void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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uint64_t param)
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{
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CPUState *cs = ENV_GET_CPU(env);
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if (likely(!(env->hflags & HF_SVMI_MASK))) {
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return;
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}
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@ -487,7 +506,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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case SVM_EXIT_MSR:
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if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) {
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/* FIXME: this should be read in at vmrun (faster this way?) */
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uint64_t addr = ldq_phys(env->vm_vmcb +
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uint64_t addr = ldq_phys(cs->as, env->vm_vmcb +
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offsetof(struct vmcb,
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control.msrpm_base_pa));
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uint32_t t0, t1;
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@ -513,7 +532,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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t1 = 0;
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break;
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}
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if (ldub_phys(addr + t1) & ((1 << param) << t0)) {
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if (ldub_phys(cs->as, addr + t1) & ((1 << param) << t0)) {
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helper_vmexit(env, type, param);
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}
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}
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@ -535,9 +554,10 @@ void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
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uint32_t next_eip_addend)
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{
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CPUState *cs = ENV_GET_CPU(env);
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if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) {
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/* FIXME: this should be read in at vmrun (faster this way?) */
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uint64_t addr = ldq_phys(env->vm_vmcb +
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uint64_t addr = ldq_phys(cs->as, env->vm_vmcb +
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offsetof(struct vmcb, control.iopm_base_pa));
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uint16_t mask = (1 << ((param >> 4) & 7)) - 1;
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@ -559,7 +579,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016"
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PRIx64 ", " TARGET_FMT_lx ")!\n",
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exit_code, exit_info_1,
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ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
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control.exit_info_2)),
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env->eip);
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@ -625,29 +645,33 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
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cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
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env->tsc_offset = 0;
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env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
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env->gdt.base = ldq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
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save.gdtr.base));
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env->gdt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
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save.gdtr.limit));
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env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
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env->idt.base = ldq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
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save.idtr.base));
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env->idt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
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save.idtr.limit));
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cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
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cpu_x86_update_cr0(env, ldq_phys(cs->as,
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env->vm_hsave + offsetof(struct vmcb,
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save.cr0)) |
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CR0_PE_MASK);
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cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
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cpu_x86_update_cr4(env, ldq_phys(cs->as,
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env->vm_hsave + offsetof(struct vmcb,
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save.cr4)));
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cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
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cpu_x86_update_cr3(env, ldq_phys(cs->as,
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env->vm_hsave + offsetof(struct vmcb,
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save.cr3)));
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/* we need to set the efer after the crs so the hidden flags get
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set properly */
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cpu_load_efer(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
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cpu_load_efer(env, ldq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
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save.efer)));
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env->eflags = 0;
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cpu_load_eflags(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
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cpu_load_eflags(env, ldq_phys(cs->as,
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env->vm_hsave + offsetof(struct vmcb,
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save.rflags)),
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~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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CC_OP = CC_OP_EFLAGS;
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@ -661,14 +685,17 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
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svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
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R_DS);
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env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
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env->regs[R_ESP] = ldq_phys(env->vm_hsave +
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env->eip = ldq_phys(cs->as,
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env->vm_hsave + offsetof(struct vmcb, save.rip));
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env->regs[R_ESP] = ldq_phys(cs->as, env->vm_hsave +
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offsetof(struct vmcb, save.rsp));
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env->regs[R_EAX] = ldq_phys(env->vm_hsave +
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env->regs[R_EAX] = ldq_phys(cs->as, env->vm_hsave +
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offsetof(struct vmcb, save.rax));
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env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
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env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));
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env->dr[6] = ldq_phys(cs->as,
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env->vm_hsave + offsetof(struct vmcb, save.dr6));
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env->dr[7] = ldq_phys(cs->as,
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env->vm_hsave + offsetof(struct vmcb, save.dr7));
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/* other setups */
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cpu_x86_set_cpl(env, 0);
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