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cadence_gem: Add the num-priority-queues property

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The Cadence GEM hardware supports N number priority queues, this patch is a
step towards that by adding the property to set the queues. At the moment
behaviour doesn't change as we only use queue 0.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 6543ec0d0c4bfd2678d0ed683efb197e91b17733.1469727764.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alistair Francis 2016-09-22 18:13:07 +01:00 • committed by Peter Maydell
parent bcb39a65f1
commit 2bf57f73e3
2 changed files with 64 additions and 43 deletions
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13
include/hw/net/cadence_gem.h
View file

@ -32,6 +32,8 @@
#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
#define MAX_PRIORITY_QUEUES 8
typedef struct CadenceGEMState {
/*< private >*/
SysBusDevice parent_obj;
@ -40,7 +42,10 @@ typedef struct CadenceGEMState {
MemoryRegion iomem;
NICState *nic;
NICConf conf;
qemu_irq irq;
qemu_irq irq[MAX_PRIORITY_QUEUES];
/* Static properties */
uint8_t num_priority_queues;
/* GEM registers backing store */
uint32_t regs[CADENCE_GEM_MAXREG];
@ -59,12 +64,12 @@ typedef struct CadenceGEMState {
uint8_t phy_loop; /* Are we in phy loopback? */
/* The current DMA descriptor pointers */
uint32_t rx_desc_addr;
uint32_t tx_desc_addr;
uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
uint8_t can_rx_state; /* Debug only */
unsigned rx_desc[2];
unsigned rx_desc[MAX_PRIORITY_QUEUES][2];
bool sar_active[4];
} CadenceGEMState;