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target/arm: Remove now-unused vfp.fp_status and FPST_FPCR

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Now we have moved all the uses of vfp.fp_status and FPST_FPCR
to either the A32 or A64 fields, we can remove these.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-13-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2025-01-24 16:27:32 +00:00
parent e107a7a54e
commit 2aa9656ebc
4 changed files with 1 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

1
target/arm/cpu.c
View file

@ -572,7 +572,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
arm_set_default_fp_behaviours(&env->vfp.fp_status);
arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status);

2
target/arm/cpu.h
View file

@ -633,7 +633,6 @@ typedef struct CPUArchState {
/* There are a number of distinct float control structures:
*
* fp_status: is the "normal" fp status.
* fp_status_a32: is the "normal" fp status for AArch32 insns
* fp_status_a64: is the "normal" fp status for AArch64 insns
* fp_status_fp16: used for half-precision calculations
@ -660,7 +659,6 @@ typedef struct CPUArchState {
* only thing which needs to read the exception flags being
* an explicit FPSCR read.
*/
float_status fp_status;
float_status fp_status_a32;
float_status fp_status_a64;
float_status fp_status_f16;

6
target/arm/tcg/translate.h
View file

@ -670,7 +670,6 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
* Enum for argument to fpstatus_ptr().
*/
typedef enum ARMFPStatusFlavour {
FPST_FPCR,
FPST_A32,
FPST_A64,
FPST_FPCR_F16,
@ -686,8 +685,6 @@ typedef enum ARMFPStatusFlavour {
* been set up to point to the requested field in the CPU state struct.
* The options are:
*
* FPST_FPCR
* for non-FP16 operations controlled by the FPCR
* FPST_A32
* for AArch32 non-FP16 operations controlled by the FPCR
* FPST_A64
@ -705,9 +702,6 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
int offset;
switch (flavour) {
case FPST_FPCR:
offset = offsetof(CPUARMState, vfp.fp_status);
break;
case FPST_A32:
offset = offsetof(CPUARMState, vfp.fp_status_a32);
break;

8
target/arm/vfp_helper.c
View file

@ -61,9 +61,8 @@ static inline uint32_t vfp_exceptbits_from_host(int host_bits)
static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
{
uint32_t i;
uint32_t i = 0;
i = get_float_exception_flags(&env->vfp.fp_status);
i |= get_float_exception_flags(&env->vfp.fp_status_a32);
i |= get_float_exception_flags(&env->vfp.fp_status_a64);
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
@ -82,7 +81,6 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env)
* values. The caller should have arranged for env->vfp.fpsr to
* be the architecturally up-to-date exception flag information first.
*/
set_float_exception_flags(0, &env->vfp.fp_status);
set_float_exception_flags(0, &env->vfp.fp_status_a32);
set_float_exception_flags(0, &env->vfp.fp_status_a64);
set_float_exception_flags(0, &env->vfp.fp_status_f16);
@ -112,7 +110,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
i = float_round_to_zero;
break;
}
set_float_rounding_mode(i, &env->vfp.fp_status);
set_float_rounding_mode(i, &env->vfp.fp_status_a32);
set_float_rounding_mode(i, &env->vfp.fp_status_a64);
set_float_rounding_mode(i, &env->vfp.fp_status_f16);
@ -126,8 +123,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
}
if (changed & FPCR_FZ) {
bool ftz_enabled = val & FPCR_FZ;
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
@ -135,7 +130,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
}
if (changed & FPCR_DN) {
bool dnan_enabled = val & FPCR_DN;
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);