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ETRAX-SER: Untabify.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Edgar E. Iglesias
parent
4b816985b8
commit
2a9859e724
1 changed files with 89 additions and 89 deletions
178
hw/etraxfs_ser.c
178
hw/etraxfs_ser.c
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@ -45,115 +45,115 @@
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struct etrax_serial
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struct etrax_serial
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{
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{
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SysBusDevice busdev;
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SysBusDevice busdev;
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CharDriverState *chr;
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CharDriverState *chr;
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qemu_irq irq;
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qemu_irq irq;
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/* This pending thing is a hack. */
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/* This pending thing is a hack. */
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int pending_tx;
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int pending_tx;
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/* Control registers. */
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/* Control registers. */
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uint32_t regs[R_MAX];
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uint32_t regs[R_MAX];
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};
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};
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static void ser_update_irq(struct etrax_serial *s)
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static void ser_update_irq(struct etrax_serial *s)
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{
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{
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s->regs[R_INTR] &= ~(s->regs[RW_ACK_INTR]);
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s->regs[R_INTR] &= ~(s->regs[RW_ACK_INTR]);
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s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
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s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
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qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
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qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
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s->regs[RW_ACK_INTR] = 0;
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s->regs[RW_ACK_INTR] = 0;
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}
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}
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static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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{
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{
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struct etrax_serial *s = opaque;
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struct etrax_serial *s = opaque;
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D(CPUState *env = s->env);
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D(CPUState *env = s->env);
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uint32_t r = 0;
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uint32_t r = 0;
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addr >>= 2;
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addr >>= 2;
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switch (addr)
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switch (addr)
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{
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{
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case R_STAT_DIN:
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case R_STAT_DIN:
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r = s->regs[RS_STAT_DIN];
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r = s->regs[RS_STAT_DIN];
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break;
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break;
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case RS_STAT_DIN:
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case RS_STAT_DIN:
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r = s->regs[addr];
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r = s->regs[addr];
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/* Read side-effect: clear dav. */
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/* Read side-effect: clear dav. */
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s->regs[addr] &= ~(1 << STAT_DAV);
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s->regs[addr] &= ~(1 << STAT_DAV);
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break;
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break;
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default:
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default:
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r = s->regs[addr];
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r = s->regs[addr];
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D(printf ("%s %x=%x\n", __func__, addr, r));
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D(printf ("%s %x=%x\n", __func__, addr, r));
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break;
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break;
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}
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}
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return r;
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return r;
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}
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}
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static void
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static void
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ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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{
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struct etrax_serial *s = opaque;
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struct etrax_serial *s = opaque;
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unsigned char ch = value;
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unsigned char ch = value;
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D(CPUState *env = s->env);
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D(CPUState *env = s->env);
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D(printf ("%s %x %x\n", __func__, addr, value));
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D(printf ("%s %x %x\n", __func__, addr, value));
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addr >>= 2;
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addr >>= 2;
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switch (addr)
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switch (addr)
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{
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{
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case RW_DOUT:
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case RW_DOUT:
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qemu_chr_write(s->chr, &ch, 1);
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qemu_chr_write(s->chr, &ch, 1);
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s->regs[R_INTR] |= 1;
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s->regs[R_INTR] |= 1;
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s->pending_tx = 1;
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s->pending_tx = 1;
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s->regs[addr] = value;
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s->regs[addr] = value;
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break;
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break;
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case RW_ACK_INTR:
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case RW_ACK_INTR:
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s->regs[addr] = value;
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s->regs[addr] = value;
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if (s->pending_tx && (s->regs[addr] & 1)) {
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if (s->pending_tx && (s->regs[addr] & 1)) {
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s->regs[R_INTR] |= 1;
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s->regs[R_INTR] |= 1;
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s->pending_tx = 0;
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s->pending_tx = 0;
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s->regs[addr] &= ~1;
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s->regs[addr] &= ~1;
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}
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}
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break;
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break;
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default:
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default:
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s->regs[addr] = value;
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s->regs[addr] = value;
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break;
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break;
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}
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}
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ser_update_irq(s);
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ser_update_irq(s);
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}
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}
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static CPUReadMemoryFunc *ser_read[] = {
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static CPUReadMemoryFunc *ser_read[] = {
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NULL, NULL,
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NULL, NULL,
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&ser_readl,
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&ser_readl,
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};
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};
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static CPUWriteMemoryFunc *ser_write[] = {
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static CPUWriteMemoryFunc *ser_write[] = {
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NULL, NULL,
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NULL, NULL,
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&ser_writel,
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&ser_writel,
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};
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};
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static void serial_receive(void *opaque, const uint8_t *buf, int size)
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static void serial_receive(void *opaque, const uint8_t *buf, int size)
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{
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{
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struct etrax_serial *s = opaque;
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struct etrax_serial *s = opaque;
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s->regs[R_INTR] |= 8;
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s->regs[R_INTR] |= 8;
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s->regs[RS_STAT_DIN] &= ~0xff;
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s->regs[RS_STAT_DIN] &= ~0xff;
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s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);
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s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);
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s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav. */
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s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav. */
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ser_update_irq(s);
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ser_update_irq(s);
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}
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}
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static int serial_can_receive(void *opaque)
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static int serial_can_receive(void *opaque)
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{
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{
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struct etrax_serial *s = opaque;
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struct etrax_serial *s = opaque;
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int r;
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int r;
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/* Is the receiver enabled? */
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/* Is the receiver enabled? */
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r = s->regs[RW_REC_CTRL] & 1;
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r = s->regs[RW_REC_CTRL] & 1;
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/* Pending rx data? */
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/* Pending rx data? */
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r |= !(s->regs[R_INTR] & 8);
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r |= !(s->regs[R_INTR] & 8);
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return r;
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return r;
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}
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}
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static void serial_event(void *opaque, int event)
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static void serial_event(void *opaque, int event)
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@ -163,27 +163,27 @@ static void serial_event(void *opaque, int event)
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static void etraxfs_ser_init(SysBusDevice *dev)
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static void etraxfs_ser_init(SysBusDevice *dev)
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{
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{
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struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
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struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
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int ser_regs;
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int ser_regs;
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/* transmitter begins ready and idle. */
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/* transmitter begins ready and idle. */
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s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
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s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
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s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
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s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(dev, &s->irq);
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ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
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ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
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sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
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sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
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s->chr = qdev_init_chardev(&dev->qdev);
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s->chr = qdev_init_chardev(&dev->qdev);
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if (s->chr)
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if (s->chr)
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qemu_chr_add_handlers(s->chr,
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qemu_chr_add_handlers(s->chr,
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serial_can_receive, serial_receive,
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serial_can_receive, serial_receive,
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serial_event, s);
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serial_event, s);
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}
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}
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static void etraxfs_serial_register(void)
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static void etraxfs_serial_register(void)
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{
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{
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sysbus_register_dev("etraxfs,serial", sizeof (struct etrax_serial),
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sysbus_register_dev("etraxfs,serial", sizeof (struct etrax_serial),
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etraxfs_ser_init);
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etraxfs_ser_init);
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}
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}
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device_init(etraxfs_serial_register)
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device_init(etraxfs_serial_register)
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