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target-mips: make CP0_LLAddr register CPU dependent

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Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
This commit is contained in:
Aurelien Jarno 2009-11-22 13:22:54 +01:00
parent 5499b6ffac
commit 2a6e32dd46
5 changed files with 49 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

7
target-mips/translate.c
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@ -3841,7 +3841,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 17:
switch (sel) {
case 0:
/* ignored */
gen_helper_mtc0_lladdr(arg);
rn = "LLAddr";
break;
default:
@ -4998,7 +4998,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 17:
switch (sel) {
case 0:
/* ignored */
gen_helper_mtc0_lladdr(arg);
rn = "LLAddr";
break;
default:
@ -8633,6 +8633,9 @@ void cpu_reset (CPUMIPSState *env)
env->CP0_Config3 = env->cpu_model->CP0_Config3;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
<< env->cpu_model->CP0_LLAddr_shift;
env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
env->SYNCI_Step = env->cpu_model->SYNCI_Step;
env->CCRes = env->cpu_model->CCRes;
env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;