motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-02 23:33:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target-mips: make CP0_LLAddr register CPU dependent

Browse source 
Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
This commit is contained in:
Aurelien Jarno 2009-11-22 13:22:54 +01:00
parent 5499b6ffac
commit 2a6e32dd46
5 changed files with 49 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

11
target-mips/op_helper.c
View file

@ -730,7 +730,7 @@ target_ulong helper_mftc0_status(void)
target_ulong helper_mfc0_lladdr (void)
{
return (int32_t)env->lladdr >> 4;
return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
}
target_ulong helper_mfc0_watchlo (uint32_t sel)
@ -795,7 +795,7 @@ target_ulong helper_dmfc0_tcschefback (void)
target_ulong helper_dmfc0_lladdr (void)
{
return env->lladdr >> 4;
return env->lladdr >> env->CP0_LLAddr_shift;
}
target_ulong helper_dmfc0_watchlo (uint32_t sel)
@ -1243,6 +1243,13 @@ void helper_mtc0_config2 (target_ulong arg1)
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
}
void helper_mtc0_lladdr (target_ulong arg1)
{
target_long mask = env->CP0_LLAddr_rw_bitmask;
arg1 = arg1 << env->CP0_LLAddr_shift;
env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
}
void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
{
/* Watch exceptions for instructions, data loads, data stores