motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 07:43:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

apb: use gpios to wire up the apb device to the SPARC CPU IRQs

Browse source 
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
This commit is contained in:
Mark Cave-Ayland 2017-12-21 07:32:57 +00:00
parent 588978c0a1
commit 2a4d6af51b
5 changed files with 18 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

6
include/hw/pci-host/apb.h
View file

@ -50,6 +50,8 @@ typedef struct IOMMUState {
uint64_t regs[IOMMU_NREGS];
} IOMMUState;
#define MAX_IVEC 0x40
#define TYPE_APB "pbm"
#define APB_DEVICE(obj) \
@ -71,7 +73,7 @@ typedef struct APBState {
uint32_t pci_err_irq_map[4];
uint32_t obio_irq_map[32];
qemu_irq *pbm_irqs;
qemu_irq *ivec_irqs;
qemu_irq ivec_irqs[MAX_IVEC];
unsigned int irq_request;
uint32_t reset_control;
unsigned int nr_resets;
@ -91,5 +93,5 @@ typedef struct PBMPCIBridge {
APBState *pci_apb_init(hwaddr special_base,
hwaddr mem_base,
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3);
PCIBus **bus2, PCIBus **bus3);
#endif